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    Power management of instruction processors in a system-on-a-chip
    101.
    发明授权
    Power management of instruction processors in a system-on-a-chip 有权

    公开(公告)号：US10133574B2

    公开(公告)日：2018-11-20

    申请号：US15181837

    申请日：2016-06-14

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Akanksha Jain ,  Wei Huang ,  Indrani Paul

    IPC: G06F9/30 ,  G06F1/32

    Abstract: A system-on-a-chip includes a plurality of instruction processors and a hardware block such as a system management unit. The hardware block accesses values of performance counters associated with the plurality of instruction processors and modifies one or more operating points of one or more of the plurality of instruction processors based on comparisons of the instruction arrival rates and the instruction service rates to achieve optimized system metrics.

    System and method for determining concurrency factors for dispatch size of parallel processor kernels
    102.
    发明授权
    System and method for determining concurrency factors for dispatch size of parallel processor kernels 有权

    公开(公告)号：US09965343B2

    公开(公告)日：2018-05-08

    申请号：US14710879

    申请日：2015-05-13

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Rathijit Sen ,  Indrani Paul ,  Wei Huang

    IPC: G06F9/54 ,  G06F9/445

    CPC classification number: G06F9/545 ,  G06F9/44505 ,  Y02D10/43

    Abstract: Disclosed is a method of determining concurrency factors for an application running on a parallel processor. Also disclosed is a system for implementing the method. In an embodiment, the method includes running at least a portion of the kernel as sequences of mini-kernels, each mini-kernel including a number of concurrently executing workgroups. The number of concurrently executing workgroups is defined as a concurrency factor of the mini-kernel. A performance measure is determined for each sequence of mini-kernels. From the sequences, a particular sequence is chosen that achieves a desired performance of the kernel, based on the performance measures. The kernel is executed with the particular sequence.

    Decoupled selective implementation of entry and exit prediction for power gating processor components
    106.
    发明授权
    Decoupled selective implementation of entry and exit prediction for power gating processor components 有权
    电源门控处理器组件的进入和退出预测的去耦选择性实现

    公开(公告)号：US09507410B2

    公开(公告)日：2016-11-29

    申请号：US14310908

    申请日：2014-06-20

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Yasuko Eckert ,  Manish Arora ,  Indrani Paul

    IPC: G06F1/32

    CPC classification number: G06F1/3296 ,  G06F1/3228 ,  G06F1/3287 ,  G06F1/3293 ,  G06N5/04 ,  Y02D10/171 ,  Y02D50/20

    Abstract: Power gating logic detects a transition of a component of a processing device into an idle state. In response to detecting the transition, the entry/exit power gating logic selectively implements one or more entry prediction techniques for power gating the component based on estimates of reliability of the entry prediction techniques. The entry/exit power gating logic also selectively implements one or more exit prediction techniques for exiting the power gated state based on estimates of reliability of the exit prediction techniques.

    Abstract translation: 电源门控逻辑检测处理设备的组件转换到空闲状态。 响应于检测到转换，入口/出口功率门控逻辑基于入口预测技术的可靠性的估计，选择性地实现用于功率门控组件的一个或多个入口预测技术。 入口/出口电力门控逻辑还基于对退出预测技术的可靠性的估计，选择性地实现一个或多个退出预测技术以退出电力门控状态。

    THERMAL AWARE DATA PLACEMENT AND COMPUTE DISPATCH IN A MEMORY SYSTEM
    107.
    发明申请
    THERMAL AWARE DATA PLACEMENT AND COMPUTE DISPATCH IN A MEMORY SYSTEM 有权
    热记录数据放置和记忆系统中的计算机分配

    公开(公告)号：US20160086654A1

    公开(公告)日：2016-03-24

    申请号：US14492045

    申请日：2014-09-21

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Manish Arora ,  Indrani Paul ,  Yasuko Eckert ,  Nuwan Jayasena ,  Dong Ping Zhang

    IPC: G11C11/4096 ,  G11C5/02 ,  G11C11/4078

    CPC classification number: G11C11/4096 ,  G11C5/025 ,  G11C7/04 ,  G11C8/12

    Abstract: A method of managing thermal levels in a memory system may include determining an expected thermal level associated with each of a plurality of locations in a memory structure, and for each operation of a plurality of operations addressed to the memory structure, assigning the operation to a target location of the plurality of physical locations in the memory structure based on a thermal penalty associated with the operation and the expected thermal level associated with the target location.

    Abstract translation: 管理存储器系统中的热水平的方法可以包括确定与存储器结构中的多个位置中的每一个相关联的预期热水平，以及针对存储器结构的多个操作的每个操作，将操作分配给 基于与操作相关联的热惩罚和与目标位置相关联的预期热水平，存储器结构中的多个物理位置的目标位置。

    POWER AND PERFORMANCE MANAGEMENT OF ASYNCHRONOUS TIMING DOMAINS IN A PROCESSING DEVICE
    108.
    发明申请
    POWER AND PERFORMANCE MANAGEMENT OF ASYNCHRONOUS TIMING DOMAINS IN A PROCESSING DEVICE 审中-公开
    异步时序域在处理设备中的功率和性能管理

    公开(公告)号：US20160077545A1

    公开(公告)日：2016-03-17

    申请号：US14489130

    申请日：2014-09-17

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Wayne P. Burleson ,  Manish Arora ,  Indrani Paul ,  Yasuko Eckert

    IPC: G06F1/08 ,  G06F1/26

    CPC classification number: G06F1/12 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    Abstract: A processing device includes a producing processor unit in a first timing domain and a consuming processor unit in a second timing domain that is asynchronous with the first timing domain. A queue is used to convey data between the producing processor unit and the consuming processor unit. A system management unit is to modify one or both of an operating frequency or an operating voltage of one or both of the producing processor unit or the consuming processor unit based on a rate of change of a fullness of the queue.

    Abstract translation: 处理装置包括在第一定时域中的产生处理器单元和与第一定时域异步的第二定时域中的消耗处理器单元。 队列用于在生成处理器单元和消费处理器单元之间传送数据。 系统管理单元基于队列的丰满度的变化率来修改生成处理器单元或消费处理器单元中的一个或两个的操作频率或工作电压中的一个或两个。

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