公开(公告)号：US20100074985A1

公开(公告)日：2010-03-25

申请号：US12236346

申请日：2008-09-23

Applicant: Chih-Hao Huang ,  Chien-Hung Liu

Inventor： Chih-Hao Huang ,  Chien-Hung Liu

IPC: B29C45/07

CPC classification number: B29C45/1781

Abstract: An auxiliary position apparatus is adapted for an injection molding machine which includes a nose and the nose has a nozzle at one end thereof. The auxiliary position apparatus includes a position device for being mounted to the nose and at least two light emitting devices adjustably mounted to the position device. The two light emitting devices can emit two adjustable light beams to focus as a light-spot which is substantially in alignment with the nozzle on a mold placed on the injection molding machine. By moving the mold to make the light-spot located at an injecting hole of the mold, the nozzle can be adjustably in alignment with the injecting hole rapidly and precisely before the injection molding operations.

Abstract translation: 辅助位置装置适用于包括鼻子的注射成型机，鼻子的一端具有喷嘴。 辅助位置装置包括用于安装到鼻子的位置装置和可调节地安装到位置装置的至少两个发光装置。 两个发光器件可以发射两个可调节的光束，作为在喷射成型机上放置的模具上与喷嘴基本上对齐的光点。 通过移动模具使得光点位于模具的注入孔处，喷嘴可以在注塑操作之前快速且精确地可调节地与注入孔对准。

公开(公告)号：US07608504B2

公开(公告)日：2009-10-27

申请号：US11468311

申请日：2006-08-30

Applicant: Chien-Hung Liu ,  Shou-Wei Huang ,  Ying-Tso Chen ,  Yu-Tsung Lin

Inventor： Chien-Hung Liu ,  Shou-Wei Huang ,  Ying-Tso Chen ,  Yu-Tsung Lin

IPC: H01L21/00

CPC classification number: H01L27/115 ,  H01L27/0207 ,  H01L27/11568

Abstract: A memory is provided. The memory includes a substrate, a number of parallel bit lines, a number of parallel word lines and at least a oxide-nitride-oxide (ONO) structure. The bit lines are disposed in the substrate. The word lines are disposed on the substrate. The word lines are crossed with but not perpendicular to the bit lines. The ONO structure is disposed between the word lines and the substrate.

Abstract translation: 提供记忆。 存储器包括衬底，多个并行位线，多个并行字线和至少氧化物 - 氧化物 - 氧化物（ONO）结构。 位线设置在基板中。 字线设置在基板上。 字线与位线交叉但不垂直于位线。 ONO结构设置在字线和衬底之间。

公开(公告)号：US07527360B2

公开(公告)日：2009-05-05

申请号：US11505647

申请日：2006-08-17

Applicant: Chien-Hung Liu ,  Jian-Chiun Liou ,  Chi-Ming Huang ,  Chia-Cheng Chiao ,  Chun-Jung Chen

Inventor： Chien-Hung Liu ,  Jian-Chiun Liou ,  Chi-Ming Huang ,  Chia-Cheng Chiao ,  Chun-Jung Chen

IPC: B41J2/05

CPC classification number: B41J2/1629 ,  B41J2/14129 ,  B41J2/1601 ,  B41J2/1639 ,  B41J2202/13 ,  Y10T29/49083 ,  Y10T29/49085 ,  Y10T29/49099 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49346 ,  Y10T29/49401

Abstract: A structure of inkjet-head chip and a method for making the same are disclosed. Driven by the need of making a thin insulator layer to lower the working power of the inkjet-head chip, we separately manufacture a passivation layer and a second conductive layer. The passivation layer and the second conductive layer have to be formed from different materials. The defining means for the passivation layer and the second conductive layer have high selectivity and do not overetch or damage the structure of inkjet-head chip.

Abstract translation: 公开了一种喷墨头芯片的结构及其制造方法。 由于需要制造薄的绝缘体层以降低喷墨头芯片的工作功率，我们分别制造钝化层和第二导电层。 钝化层和第二导电层必须由不同的材料形成。 用于钝化层和第二导电层的限定装置具有高选择性，并且不会破坏或损坏喷墨头芯片的结构。

公开(公告)号：US20090056983A1

公开(公告)日：2009-03-05

申请号：US11941979

申请日：2007-11-19

Applicant: Chien-Hung Liu ,  Shou-Kuo Hsu ,  Yu-Chang Pai

Inventor： Chien-Hung Liu ,  Shou-Kuo Hsu ,  Yu-Chang Pai

IPC: H05K1/02

CPC classification number: H05K1/0245 ,  H05K1/0298 ,  H05K2201/09236 ,  H05K2201/09336 ,  H05K2201/09672 ,  Y10S439/941

Abstract: A printed circuit board (PCB) includes first and second signal layers sandwiching a dielectric layer therebetween and a first differential pair and a second differential pair each having a positive differential trace and a negative differential trace. The positive differential traces of the two differential pairs are disposed within the first signal layer. The negative differential traces of the two differential pairs are disposed within the second signal layer. The positive differential trace of the first differential pair is defined at the left side of the positive differential trace of the second differential pair. The negative differential trace of the first differential pair is defined at the right side of the negative differential trace of the second differential pair.

Abstract translation: 印刷电路板（PCB）包括夹在其间的电介质层的第一和第二信号层，以及分别具有正差分迹线和负差分迹线的第一差分对和第二差分对。 两个差分对的正差分迹线设置在第一信号层内。 两个差分对的负差分迹线设置在第二信号层内。 第一差分对的正差分迹线被定义在第二差分对的正差分迹线的左侧。 第一差分对的负差分迹线被限定在第二差分对的负差分迹线的右侧。

公开(公告)号：US07358184B2

公开(公告)日：2008-04-15

申请号：US10819137

申请日：2004-04-07

Applicant: Chien-Hung Liu ,  Ming-Huan Yang ,  Jane Chang ,  Chun-Jung Chen ,  Chao-Kai Cheng ,  Kou-Chen Liu

Inventor： Chien-Hung Liu ,  Ming-Huan Yang ,  Jane Chang ,  Chun-Jung Chen ,  Chao-Kai Cheng ,  Kou-Chen Liu

IPC: H01L21/44

CPC classification number: H01L29/66742 ,  H01L21/288 ,  H01L21/76802 ,  H01L21/76838 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66765 ,  H05K3/002 ,  H05K3/4069 ,  H05K2203/013 ,  H05K2203/0783

Abstract: A method of forming a conductive via plug is disclosed. The conductive via plug is formed by printing a solution comprising a solvent with insulating material dissolve capability and a conductive material by an inkjet method. The formed conductive via plug has a low resistivity and thus may serve as an electrical connection between two separate conductive layers. This manufacturing method of the conductive via plug may achieve simultaneously deposition, patterning and etching purposes, which significantly simplifies the manufacturing process.

Abstract translation: 公开了形成导电通孔的方法。 导电通孔插塞是通过用喷墨法印刷包含具有绝缘材料溶剂的溶剂的溶液和导电材料而形成的。 所形成的导电通孔塞具有低电阻率，因此可以用作两个分开的导电层之间的电连接。 导电通孔插头的这种制造方法可以实现同时沉积，图案化和蚀刻目的，这显着简化了制造工艺。

公开(公告)号：US20070269943A1

公开(公告)日：2007-11-22

申请号：US11435458

申请日：2006-05-16

Applicant: Chin-Hsien Chen ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shou-Wei Huang

Inventor： Chin-Hsien Chen ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shou-Wei Huang

IPC: H01L21/8234

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/7881 ,  H01L29/792

Abstract: A method of fabricating a non-volatile memory is provided. First, two openings are formed on a substrate. A stacked gate structure comprising a first dielectric layer, a charge storage layer, a second dielectric layer and a first conductive layer is formed on the substrate between the two openings. A liner is formed on a bottom and a portion of a sidewall of the tow openings, wherein a top surface of the liner is lower than that of the substrate. A second conductive layer is formed on the liner at the bottom of the two openings, wherein a top surface of the second conductive layer is co-planar with that of the liner. A third conductive layer is formed on the second conductive layer and the liner, wherein a top surface of the third conductive layer is co-planar with that of the substrate and lower than that of the first dielectric layer.

Abstract translation: 提供了一种制造非易失性存储器的方法。 首先，在基板上形成两个开口。 在两个开口之间的基板上形成包括第一电介质层，电荷存储层，第二电介质层和第一导电层的堆叠栅极结构。 衬套形成在丝束开口的侧壁的底部和一部分上，其中衬垫的顶表面低于衬底的顶表面。 第二导电层形成在两个开口的底部的衬垫上，其中第二导电层的顶表面与衬垫的顶表面共面。 第三导电层形成在第二导电层和衬垫上，其中第三导电层的顶表面与衬底的顶表面平行，并且低于第一介电层的顶表面。

公开(公告)号：US07134187B2

公开(公告)日：2006-11-14

申请号：US10860240

申请日：2004-06-03

Applicant: Chien-Hung Liu ,  Jian-Chiun Liou ,  Chi-Ming Huang ,  Chia-Cheng Chiao ,  Chun-Jung Chen

Inventor： Chien-Hung Liu ,  Jian-Chiun Liou ,  Chi-Ming Huang ,  Chia-Cheng Chiao ,  Chun-Jung Chen

IPC: H05B3/00

CPC classification number: B41J2/1629 ,  B41J2/14129 ,  B41J2/1601 ,  B41J2/1639 ,  B41J2202/13 ,  Y10T29/49083 ,  Y10T29/49085 ,  Y10T29/49099 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49346 ,  Y10T29/49401

Abstract: A structure of inkjet-head chip and a method for making the same are disclosed. Driven by the need of making a thin insulator layer to lower the working power of the inkjet-head chip, we separately manufacture a passivation layer and a second conductive layer. The passivation layer and the second conductive layer have to be formed from different materials. The defining means for the passivation layer and the second conductive layer have high selectivity and do not overetch or damage the structure of inkjet-head chip.

Abstract translation: 公开了一种喷墨头芯片的结构及其制造方法。 由于需要制造薄的绝缘体层以降低喷墨头芯片的工作功率，我们分别制造钝化层和第二导电层。 钝化层和第二导电层必须由不同的材料形成。 用于钝化层和第二导电层的限定装置具有高选择性，并且不会破坏或损坏喷墨头芯片的结构。

公开(公告)号：US20050045582A1

公开(公告)日：2005-03-03

申请号：US10702555

申请日：2003-11-07

Applicant: Chi-Ming Huang ,  Chia-Tai Chen ,  Yu-Hung Chuang ,  Jian-Chiun Lion ,  Chien-Hung Liu ,  Chun-Jung Chen

Inventor： Chi-Ming Huang ,  Chia-Tai Chen ,  Yu-Hung Chuang ,  Jian-Chiun Lion ,  Chien-Hung Liu ,  Chun-Jung Chen

IPC: B41J2/16 ,  H05K3/00 ,  H05K3/20 ,  G11B5/127

CPC classification number: B41J2/16 ,  B41J2/1625 ,  B41J2/1626 ,  B41J2/1631 ,  B41J2/1639 ,  H05K3/0023 ,  H05K3/205 ,  H05K2201/09063 ,  H05K2201/0969

Abstract: A component for the inkjet print head and the manufacturing method thereof are disclosed where photosensitive polymer is used as the substrate. Orifices and ink chambers are made on the substrate by photolithography. Conductive traces for interconnection to a print head chip are integrated to the substrate by combining photolithography and electroforming procedures.

Abstract translation: 公开了一种用于喷墨打印头的部件及其制造方法，其中使用光敏聚合物作为基底。 通过光刻在基板上制造孔和墨室。 用于与打印头芯片互连的导电迹线通过组合光刻和电铸工艺而集成到衬底中。

公开(公告)号：US06794701B2

公开(公告)日：2004-09-21

申请号：US10616083

申请日：2003-07-08

Applicant: Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

Inventor： Tung-Cheng Kuo ,  Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

IPC: H01L27108

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L21/743 ,  H01L21/76892 ,  H01L27/115 ,  H01L29/66833

Abstract: A non-volatile memory and the fabrication thereof are described. The non-volatile memory comprises a word-line on a substrate, a charge trapping layer between the word-line and the substrate, and a contact electrically connecting with the word-line over the substrate. In addition, there is a protective metal line electrically connecting with the word-line and with a grounding doped region in the substrate via different contacts, respectively. The protective metal line has a resistance higher than that of the word-line.

Abstract translation: 描述非易失性存储器及其制造。 非易失性存储器包括衬底上的字线，字线和衬底之间的电荷俘获层，以及与衬底上的字线电连接的触点。 此外，存在与字线电连接的保护金属线和分别经由不同触点的衬底中的接地掺杂区域。 保护金属线的电阻比字线高。

公开(公告)号：USD487457S1

公开(公告)日：2004-03-09

申请号：US29176987

申请日：2003-03-04

Applicant: Chien-Hung Liu

Designer： Chien-Hung Liu