公开(公告)号：US10147802B2

公开(公告)日：2018-12-04

申请号：US15160591

申请日：2016-05-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Manfred Eller ,  Min-hwa Chi

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L27/11 ,  H01L27/12 ,  H01L27/02

Abstract: Circuit structures, such as inverters and static random access memories, and fabrication methods thereof are presented. The circuit structures include, for instance: a first transistor, the first transistor having a first channel region disposed above an isolation region; and a second transistor, the second transistor having a second channel region, the second channel region being laterally adjacent to the first channel region of the first transistor and vertically spaced apart therefrom by the isolation region thereof. In one embodiment, the first channel region and the isolation region of the first transistor are disposed above a substrate, and the substrate includes the second channel region of the second transistor. In another embodiment, the first transistor includes a fin structure extending from the substrate, and an upper portion of the fin structure includes the first channel region and a lower portion of the fin structure includes the isolation region.

公开(公告)号：US10128333B2

公开(公告)日：2018-11-13

申请号：US15627973

申请日：2017-06-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hoong Shing Wong ,  Min-hwa Chi ,  Tae-Hoon Kim

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: A FinFET has shaped epitaxial structures for the source and drain that are electrically isolated from the substrate. Shaped epitaxial structures in the active region are separated from the substrate in the source and drain regions while those in the channel region remain. The gaps created by the separation in the source and drain are filled with electrically insulating material. Prior to filling the gaps, defects created by the separation may be reduced.

公开(公告)号：US10014303B2

公开(公告)日：2018-07-03

申请号：US15248889

申请日：2016-08-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L29/66 ,  H01L27/11 ,  H01L21/311 ,  H01L21/768 ,  H01L29/78 ,  H01L23/535

CPC classification number: H01L27/1104 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/535 ,  H01L27/11 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices for forming conductive paths between fins for contact-to-gate shorting. One method includes, for instance: obtaining wafer with a substrate, at least one fin, at least one hard mask, and an oxide layer; etching the oxide layer to reveal at least one of a portion of the hard masks; forming sacrificial pillars over the substrate; forming sacrificial gates, wherein at least one sacrificial gate contacts at least one sacrificial pillar; growing an epitaxial layer between the at least one sacrificial gate and the at least one sacrificial pillar; starting a RMG process on the sacrificial gates; etching to remove the sacrificial pillars and form pillar openings; and completing the RMG process to fill the pillar openings and the gate openings with a metal.

公开(公告)号：US09881738B2

公开(公告)日：2018-01-30

申请号：US14818342

申请日：2015-08-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01G13/00 ,  H01G4/012 ,  H01G4/30 ,  H01G4/33 ,  H01L49/02

CPC classification number: H01G4/012 ,  H01G4/306 ,  H01G4/33 ,  H01L23/5222 ,  H01L28/82 ,  H01L28/90

Abstract: Capacitor structures having first electrodes at least partially embedded within a second electrode, and fabrication methods are presented. The methods include, for instance: providing the first electrodes at least partially within an insulator layer, the first electrodes comprising exposed portions; covering exposed portions of the first electrodes with a dielectric material; and forming the second electrode at least partially around the dielectric covered portions of the first electrodes, the second electrode being physically separated from the first electrodes by the dielectric material. In one embodiment, a method further includes exposing further portions of the first electrodes; and providing a contact structure in electrical contact with the further exposed portions of the first electrodes. In another embodiment, some of the first electrodes are aligned substantially parallel to a first direction and other of the first electrodes are aligned substantially parallel to a second direction, the first and second directions being different directions.

公开(公告)号：US09831248B1

公开(公告)日：2017-11-28

申请号：US15425366

申请日：2017-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L21/00 ,  H01L27/108 ,  H01L49/02 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L27/10826 ,  H01L27/1085 ,  H01L27/10879 ,  H01L27/10885 ,  H01L27/10891 ,  H01L28/91

Abstract: A semiconductor structure includes an array of fins extending horizontally across a substrate. A plurality of transistors are embedded in the fins. The transistors include a 1st S/D region and a 2nd S/D region defining a channel region therebetween. The transistors have a gate structure disposed over the channel region and extending perpendicular to the fins. An ILD layer is disposed over the structure. The ILD layer includes a plurality of TS trenches disposed over the 1st and 2nd S/D regions. The TS tranches extend parallel to the gate structures. A plurality of storage capacitors are disposed within the TS trenches. The storage capacitors include a 1st metal terminal electrically connected to one of the 1st and 2nd S/D regions, a 2nd metal terminal and a capacitor dielectric disposed therebetween. Each transistor is electrically connected to a single storage capacitor to form an eDRAM cell.

公开(公告)号：US09754903B2

公开(公告)日：2017-09-05

申请号：US14926880

申请日：2015-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj K. Patil ,  Min-hwa Chi ,  Ajey Poovannummoottil Jacob

IPC: H01L21/00 ,  H01L23/62

CPC classification number: H01L23/62 ,  H01L23/5252

Abstract: A semiconductor structure includes a dielectric layer, a silicidable metal layer and an undoped filler material layer are used to create an anti-efuse device. The anti-efuse device may be situated in a dielectric layer of an interconnect structure for a semiconductor device or may be planar. Where part of an interconnect structure, the anti-efuse device may be realized by causing a current to flow therethrough while applying local heating. Where planar, the filler material may be situated between extensions of metal pads and metal atoms caused to move from the extensions to the filler material layer using a current flow and local heating.

公开(公告)号：US09716138B1

公开(公告)日：2017-07-25

申请号：US15075890

申请日：2016-03-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L29/06 ,  H01L29/10 ,  H01L21/762 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L21/743 ,  H01L21/76229 ,  H01L21/7624 ,  H01L21/76283 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/481 ,  H01L29/0649 ,  H01L29/1087

Abstract: Devices and methods of fabricating integrated circuit devices for dynamically applying bias to back plates and/or p-well regions are provided. One method includes, for instance: obtaining a wafer with a silicon substrate, at least one first oxide layer, at least one silicon layer, and at least one second oxide layer; forming at least one recess in the wafer; depositing at least one third oxide layer over the wafer and filling the at least one recess; depositing a silicon nitride layer over the wafer; and forming at least one opening having sidewalls and a bottom surface within the filled at least one recess. An intermediate semiconductor device is also disclosed.

公开(公告)号：US09673757B2

公开(公告)日：2017-06-06

申请号：US14156565

申请日：2014-01-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang Liu ,  Min-hwa Chi

IPC: H01L29/739 ,  H03C3/02 ,  H01L29/66 ,  H01L29/78 ,  H03C3/24 ,  H01L29/08 ,  H01L29/161

CPC classification number: H03C3/145 ,  H01L27/088 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/66356 ,  H01L29/66568 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/78 ,  H01L29/7848 ,  H03C3/02 ,  H03C3/245 ,  H03D7/125

Abstract: Tunneling field effect transistors and fabrication methods thereof are provided, which include: obtaining a gate structure disposed over a substrate structure; and providing a source region and a drain region within the substrate structure separated by a channel region, the channel region underlying, at least partially, the gate structure, and the providing including: modifying the source region to attain a narrowed source region bandgap; and modifying the drain region to attain a narrowed drain region bandgap, the narrowed source region bandgap and the narrowed drain region bandgap facilitating quantum tunneling of charge carriers from the source region or the drain region to the channel region. Devices including digital modulation circuits with one or more tunneling field effect transistor(s) are also provided.

公开(公告)号：US09583479B1

公开(公告)日：2017-02-28

申请号：US14995324

申请日：2016-01-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L29/94 ,  H01L27/02 ,  H01L49/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/311

CPC classification number: H01L27/0222 ,  G11C5/145 ,  H01L21/31105 ,  H01L21/823431 ,  H01L28/40 ,  H01L29/66181 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/785 ,  H02M3/07 ,  H02M3/073 ,  H02M2003/076

Abstract: A charge pump for an integrated circuit includes a substrate, first and second transistors and a capacitor. The first transistor includes first source and first drain regions disposed within the substrate and defining a first channel therebetween. The first source and first drain regions are implanted with one of an n-type and a p-type dopant. The second transistor includes second source and second drain regions disposed within the substrate and defining a second channel therebetween. The second source and second drain regions implanted with the same type dopant as the first source region. The capacitor includes a metal terminal and a substrate terminal with a dielectric therebetween. The substrate terminal is disposed within the substrate and implanted with the same type dopant as the first source region. The substrate terminal contacts the first drain region and second source region within the substrate to provide electrical continuity therebetween.

Abstract translation: 集成电路的电荷泵包括衬底，第一和第二晶体管和电容器。 第一晶体管包括设置在衬底内并且在其间限定第一通道的第一源极和第一漏极区域。 第一源极和第一漏极区域注入n型和p型掺杂物中的一种。 第二晶体管包括设置在衬底内并在其间限定第二通道的第二源极和第二漏极区域。 第二源极和第二漏极区域注入与第一源极区域相同类型的掺杂剂。 该电容器包括金属端子和其间具有电介质的衬底端子。 衬底端子设置在衬底内并且注入与第一源区相同类型的掺杂剂。 衬底端子接触衬底内的第一漏极区域和第二源极区域，以在它们之间提供电连续性。

公开(公告)号：US09570572B2

公开(公告)日：2017-02-14

申请号：US14523640

申请日：2014-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj K. Patil ,  Min-hwa Chi

IPC: H01L21/285 ,  H01L29/45 ,  H01L21/28 ,  H01L21/324 ,  H01L29/66

CPC classification number: H01L29/45 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/324 ,  H01L21/76843 ,  H01L21/76855 ,  H01L29/665

Abstract: There is set forth herein a method of fabricating a contact interface formation. A layer of Ti metal can be deposited on a substrate and a layer of Ni metal can be deposited over the layer of Ti metal. An annealing process can be performed to form a contact interface formation having Ti in reacted form and Ni in reacted form.

Abstract translation: 这里提出了制造接触界面形成的方法。 可以在衬底上沉积Ti金属层，并且可以在Ti金属层上沉积Ni金属层。 可以进行退火处理以形成具有反应形式的Ti和反应形式的Ni的接触界面形成。