公开(公告)号：US11588103B2

公开(公告)日：2023-02-21

申请号：US17104405

申请日：2020-11-25

Applicant: International Business Machines Corporation

Inventor： Youngseok Kim ,  Choonghyun Lee ,  Timothy Mathew Philip ,  Soon-Cheon Seo ,  Injo Ok ,  Alexander Reznicek

IPC: H01L45/00 ,  H01L27/24

Abstract: A vertical resistive memory array is presented. The array includes a pillar electrode and a switching liner around the side perimeter of the pillar electrode. The array includes two or more vertically stacked single cell (SC) electrodes connected to a first side of the switching liner. The juxtaposition of the switching liner, the pillar electrode, and each SC electrode forms respective resistance switching cells (e.g., OxRRAM cell). A vertical group or bank of these cells may be connected in parallel and each share the same pillar electrode. The cells in the vertical cell bank may written to or read from as a group to limit the effects of inconsistent CF formation of any one or more individual cells within the group.

公开(公告)号：US20220223205A1

公开(公告)日：2022-07-14

申请号：US17147401

申请日：2021-01-12

Applicant: International Business Machines Corporation

Inventor： Youngseok Kim ,  Soon-Cheon Seo ,  Choonghyun Lee ,  Injo Ok ,  Alexander Reznicek

IPC: G11C13/00 ,  H01L45/00

Abstract: An electronic circuit includes a plurality of word lines; a plurality of bit lines intersecting the plurality of word lines at a plurality of grid points; and a plurality of resistive random-access memory cells located at the plurality of grid points. Each of the resistive random-access memory cells includes a top metal coupled to one of: a corresponding one of the word lines and a corresponding one of the bit lines; a bottom metal coupled to another one of: the corresponding one of the word lines and the corresponding one of the bit lines; a dielectric sandwiched between the top metal and the bottom metal; and a high-resistance semiconductive spacer electrically connecting the top metal and the bottom metal in parallel with the dielectric.

公开(公告)号：US20220165947A1

公开(公告)日：2022-05-26

申请号：US17104405

申请日：2020-11-25

Applicant: International Business Machines Corporation

Inventor： Youngseok Kim ,  Choonghyun Lee ,  Timothy Mathew Philip ,  Soon-Cheon Seo ,  Injo Ok ,  Alexander Reznicek

IPC: H01L45/00 ,  H01L27/24

Abstract: A vertical resistive memory array is presented. The array includes a pillar electrode and a switching liner around the side perimeter of the pillar electrode. The array includes two or more vertically stacked single cell (SC) electrodes connected to a first side of the switching liner. The juxtaposition of the switching liner, the pillar electrode, and each SC electrode forms respective resistance switching cells (e.g., OxRRAM cell). A vertical group or bank of these cells may be connected in parallel and each share the same pillar electrode. The cells in the vertical cell bank may written to or read from as a group to limit the effects of inconsistent CF formation of any one or more individual cells within the group.

公开(公告)号：US11302799B2

公开(公告)日：2022-04-12

申请号：US16664060

申请日：2019-10-25

Applicant: International Business Machines Corporation

Inventor： Peng Xu ,  Choonghyun Lee ,  Kangguo Cheng ,  Juntao Li

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/8234

Abstract: A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate, forming a second semiconductor layer including a first concentration of germanium on the first semiconductor layer, and forming a third semiconductor layer on the second semiconductor layer. The first and third semiconductor layers each have a concentration of germanium, which is greater than the first concentration of germanium. The first, second and third semiconductor layers are patterned into at least one fin. The method further includes covering the second semiconductor layer with a mask layer. In the method, a bottom source/drain region and a top source/drain region are simultaneously grown from the first semiconductor layer and the third semiconductor layer, respectively. The mask layer is removed from the second semiconductor layer, and a gate structure is formed on and around the second semiconductor layer.

公开(公告)号：US20220005735A1

公开(公告)日：2022-01-06

申请号：US17475595

申请日：2021-09-15

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Choonghyun Lee ,  Juntao Li ,  Peng Xu

IPC: H01L21/8238 ,  H01L21/02 ,  H01L29/417

Abstract: Embodiments of the invention include semiconductor devices having a first n-type S/D region, a second n-type S/D region, and a first layer of protective material over the second n-type S/D region, wherein the first layer of protective material includes a first type of material and a second type of material. A second layer of protective material is formed over the first layer of protective material, wherein the second layer of protective material includes an oxide of the second type of material. The devices further include a first p-type S/D region, a second p-type S/D region, and the second layer of protective material over the second p-type S/D region, wherein the second p-type S/D region second layer of protective material includes the first type of material and the second type of material, and wherein the second layer of protective material includes the oxide of the second type of material.

公开(公告)号：US11201092B2

公开(公告)日：2021-12-14

申请号：US16366516

申请日：2019-03-27

Applicant: International Business Machines Corporation

Inventor： Injo Ok ,  Choonghyun Lee ,  Soon-Cheon Seo ,  Alexander Reznicek

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/28

Abstract: A semiconductor structure is provided utilizing a cost effective method in which the vertical gate channel length is substantially the same for vertical field effect transistors (VFETs) that are present in a dense device region and an isolated device region. The VFETs have improved uniformity, device functionality and better yield. No additional lithographic process is used in making such a semiconductor structure.

公开(公告)号：US11189661B2

公开(公告)日：2021-11-30

申请号：US16562388

申请日：2019-09-05

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Takashi Ando ,  Pouya Hashemi ,  Choonghyun Lee ,  Jingyun Zhang

IPC: H01L45/00 ,  H01L27/24 ,  H01L29/78 ,  H01L29/04 ,  H01L29/10 ,  H01L29/66 ,  H01L29/08

Abstract: A first fin field effect transistor (FinFET) has an internal source/drain (S/D) with a facetted face that is connected to a dielectric side of a first RRAM. A second FinFET and RRAM structure are also disclosed. In some embodiments, an electrode contact side of each RRAM is connected in common to form a 2T2R device. The locations of one or more electrode points on the diamond-shaped, facetted surface of the bottom electrode accurately position electric fields through the dielectric to accurately and repeatably locate where the filaments/current paths are formed (or reset) through the RRAM dielectric. Material selection and accurate thickness of the RRAM dielectric determine the voltage at which the filaments/current paths are formed (or reset).

公开(公告)号：US20210305407A1

公开(公告)日：2021-09-30

申请号：US17346869

申请日：2021-06-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jingyun Zhang ,  Choonghyun Lee ,  Chun Wing Yeung ,  Robin Hsin Kuo Chao ,  Heng Wu

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L21/3065 ,  H01L21/02

Abstract: Semiconductor devices and methods of forming the same include forming a stack of alternating first and second sacrificial layers. The first sacrificial layers are recessed relative to the second sacrificial layers. Replacement channel layers are grown from sidewalls of the first sacrificial layers. A first source/drain region is grown from the replacement channel layer. The recessed first sacrificial layers are etched away. A second source/drain region is grown from the replacement channel layer. The second sacrificial layers are etched away. A gate stack is formed between and around the replacement channel layers.

公开(公告)号：US11120991B2

公开(公告)日：2021-09-14

申请号：US16589687

申请日：2019-10-01

Applicant: International Business Machines Corporation

Inventor： Juntao Li ,  Kangguo Cheng ,  Peng Xu ,  Choonghyun Lee

IPC: H01L21/02 ,  H01L29/06 ,  H01L21/306 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L21/3065 ,  B82Y40/00 ,  H01L29/49

Abstract: A method of forming a semiconductor structure includes forming one or more fins disposed on a substrate, rounding surfaces of the one or more fins, forming faceted sidewalk from the rounded surfaces of the one or more fins, and forming a lateral semiconductor nanotube shell on the faceted sidewalk. The lateral semiconductor nanotube shell comprises a hexagonal shape.

公开(公告)号：US11094883B2

公开(公告)日：2021-08-17

申请号：US16670215

申请日：2019-10-31

Applicant: International Business Machines Corporation

Inventor： Chanro Park ,  Kangguo Cheng ,  Ruilong Xie ,  Choonghyun Lee

IPC: H01L45/00 ,  H01L27/24

Abstract: A semiconductor structure including a vertical resistive memory cell and a fabrication method therefor. The method includes forming a sacrificial layer over a transistor drain contact; forming a first dielectric layer over the sacrificial layer; forming a cell contact hole through the first dielectric layer; forming an access contact hole through the first dielectric layer and exposing the sacrificial layer; removing the sacrificial layer thereby forming a cavity connecting a bottom opening of the cell contact hole and a bottom opening of the access contact hole; forming by atomic layer deposition in the cell contact hole a second dielectric layer including a seam; forming a bottom electrode within the cavity and in contact with the drain contact, the second dielectric layer, and the seam; and forming a top electrode over the first dielectric layer and in contact with the second dielectric layer and the seam.