公开(公告)号：US20190206999A1

公开(公告)日：2019-07-04

申请号：US15861167

申请日：2018-01-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Peng Xu ,  Kangguo Cheng ,  Juntao Li ,  Heng Wu

IPC: H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/762 ,  H01L29/78 ,  H01L29/165 ,  H01L29/06

CPC classification number: H01L29/1054 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7851

Abstract: A method of a forming a plurality of semiconductor fin structures that includes forming a sacrificial gate structure on a hardmask overlying a channel region portion of the plurality of sacrificial fins of a first semiconductor material and forming source and drain regions on opposing sides of the channel region. The sacrificial gate structure and the sacrificial fin structure are removed. A second semiconductor material is formed in an opening provided by removing the sacrificial gate structure and the sacrificial fin structure. The second semiconductor material is etched selective to the hardmask to provide a plurality of second semiconductor material fin structures. A function gate structure is formed on the channel region.

公开(公告)号：US10243061B1

公开(公告)日：2019-03-26

申请号：US15814376

申请日：2017-11-15

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Juntao Li ,  Heng Wu ,  Peng Xu

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/423 ,  H01L23/31 ,  H01L23/29 ,  H01L21/02 ,  H01L21/311

Abstract: Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.

公开(公告)号：US10229985B1

公开(公告)日：2019-03-12

申请号：US15830665

申请日：2017-12-04

Applicant: International Business Machines Corporation

Inventor： Juntao Li ,  Kangguo Cheng ,  Peng Xu ,  Heng Wu

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/78

Abstract: A method of forming a semiconductor structure includes patterning two or more fins over a top surface of a bottom source/drain layer, the bottom source/drain layer disposed over a substrate. The method also includes forming bottom spacers disposed over the top surface of the bottom source/drain layer between the two or more fins, the bottom spacers having a uniform height on sidewalls of the two or more fins. The bottom spacers comprise dielectric regions disposed adjacent the sidewalls of the two or more fins and at least partially filling divots in the bottom source/drain regions, and liner regions disposed adjacent the dielectric regions. The two or more fins comprise channels for a vertical field-effect transistor (VFET) device.

公开(公告)号：US20190058045A1

公开(公告)日：2019-02-21

申请号：US15803951

申请日：2017-11-06

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Juntao Li ,  Heng Wu ,  Peng Xu

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/823481 ,  H01L21/823821 ,  H01L29/66545 ,  H01L29/6681 ,  H01L2029/7858

Abstract: Embodiments of the invention are directed to methods of forming a FinFET. A non-limiting example method includes forming a fin across from a major surface of a substrate. A dummy gate is formed around a channel region of the fin. A source region or a drain region is formed on the fin, and the dummy gate is replaced with a metal gate structure. Subsequent to replacing the dummy gate with the metal gate structure, dopants are inserted into the source region or the drain region.

公开(公告)号：US20190051736A1

公开(公告)日：2019-02-14

申请号：US16161484

申请日：2018-10-16

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Xin Miao ,  Heng Wu ,  Peng Xu

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L29/40 ,  H01L29/423

Abstract: Provided is a semiconductor structure. In one or more embodiments of the invention, a semiconductor fin on a substrate is provided. A spacer layer is on a surface of the substrate. A high dielectric constant layer is provided, wherein a first portion of the high dielectric constant layer is on sidewalls of the semiconductor fin, and a second portion of the high dielectric constant layer is over the spacer layer. A work function metal layer is on sidewalls of the semiconductor fin, wherein the work function metal layer has a uniform thickness.

公开(公告)号：US10164056B2

公开(公告)日：2018-12-25

申请号：US15597573

申请日：2017-05-17

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Xin Miao ,  Heng Wu ,  Peng Xu

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78 ,  H01L27/08 ,  H01L27/088

Abstract: Provided is a method for forming a semiconductor structure. In one or more embodiments of the invention, the method includes forming a semiconductor fin on a substrate and decreasing a width of the semiconductor fin. The method further includes forming a spacer layer on a surface of the substrate and forming a high dielectric constant layer on exposed surfaces of the semiconductor fin and the spacer layer. The method also includes forming a work function metal layer on the high dielectric constant layer. The method also includes removing portions of the work function metal layer and the high dielectric constant layer to expose portions of the spacer layer. A thickness of the remaining work function metal layer on sidewalls of the semiconductor fin is uniform.

公开(公告)号：US10134859B1

公开(公告)日：2018-11-20

申请号：US15808869

申请日：2017-11-09

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Heng Wu ,  Peng Xu

IPC: H01L21/335 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/08

Abstract: A field-effect transistor device including an asymmetric spacer assembly allows lower parasitic capacitance on the drain side of the device and lower resistance on the source side. The asymmetric spacer assembly is formed by a self-aligned process, resulting in less gate/junction overlap on the drain side of the device and greater gate/junction overlap on the source side of the device. Asymmetric transistors having small gate lengths can be obtained without overlay/misalignment issues.

公开(公告)号：US10084094B1

公开(公告)日：2018-09-25

申请号：US15462420

申请日：2017-03-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Zuoguang Liu ,  Heng Wu ,  Peng Xu

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L23/528 ,  H01L27/088

Abstract: Semiconductor device and methods of forming the same include forming a first dielectric layer over a semiconductor fin. A second dielectric layer is formed around the first dielectric layer. The semiconductor fin is recessed below a height of the first and second dielectric layers. Source and drain extensions are grown from the recessed semiconductor fin. The first dielectric layer is recessed to expose an underside of and sidewalls of the source/drain extensions. Conductive contacts are formed around exposed portions of the source/drain extensions.

公开(公告)号：US10056289B1

公开(公告)日：2018-08-21

申请号：US15492745

申请日：2017-04-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Zuoguang Liu ,  Sebastian Naczas ,  Heng Wu ,  Peng Xu

IPC: H01L27/00 ,  H01L21/764 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L21/764 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/78642 ,  H01L29/78696

Abstract: A method of forming a vertical transport fin field effect transistor with self-aligned dielectric separators, including, forming a bottom source/drain region on a substrate, forming at least two vertical fins on the bottom source/drain region, forming a protective spacer on the at least two vertical fins, forming a sacrificial liner on the protective spacer, forming an isolation channel in the bottom source/drain region and substrate between two of the at least two vertical fins, forming an insulating plug in the isolation channel, wherein the insulating plug has a pinch-off void within the isolation channel, and forming the dielectric separator on the insulating plug.

公开(公告)号：US20180212038A1

公开(公告)日：2018-07-26

申请号：US15692294

申请日：2017-08-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Robinhsinku Chao ,  ChoongHyun Lee ,  Heng Wu ,  Chun W. Yeung ,  Jingyun Zhang

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/324

CPC classification number: H01L29/66553 ,  H01L21/02247 ,  H01L21/324 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor devices and methods of forming the same include forming a layer of activating material on sidewalls of a stack of alternating layers of channel material and sacrificial material. The layer of activating material is annealed to cause the activating material to react with the sacrificial material and to form insulating spacers at ends of the layers of sacrificial material. The layer of activating material is etched away to expose ends of the layers of channel material. Source/drain regions are formed on the ends of the layers of channel material.