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    WORKLOAD-BASED SCAN OPTIMIZATION
    103.
    发明公开
    WORKLOAD-BASED SCAN OPTIMIZATION 审中-公开

    公开(公告)号：US20230305744A1

    公开(公告)日：2023-09-28

    申请号：US17691014

    申请日：2022-03-09

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Kishore Kumar Muchherla ,  Eric N. Lee ,  Jeffrey S. McNeil ,  Jonathan S. Parry ,  Lakshmi Kalpana Vakati

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679

    Abstract: A method performed by a processing device receives a plurality of write operation requests, where each of the write operation requests specifies a respective one of the memory units, identifies one or more operating characteristic values, where each operating characteristic value reflects one or more memory access operations performed on a memory device, and determines whether the operating characteristic values satisfy one or more threshold criteria. Responsive to determining that the operating characteristic values satisfy the one or more threshold criteria, the method performs a plurality of write operations, where each of the write operations writes data to the respective one of the memory units, and performs a multiple-read scan operation subsequent to the plurality of write operations, where the multiple-read scan operation reads data from each of the memory units.

    DATA BURST SUSPEND MODE USING MULTI-LEVEL SIGNALING
    104.
    发明公开
    DATA BURST SUSPEND MODE USING MULTI-LEVEL SIGNALING 审中-公开

    公开(公告)号：US20230289306A1

    公开(公告)日：2023-09-14

    申请号：US18119576

    申请日：2023-03-09

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee ,  Leonid Minz ,  Yoav Weinberg ,  Ali Feiz Zarrin Ghalam ,  Luigi Pilolli

    IPC: G06F13/30 ,  G06F13/16

    CPC classification number: G06F13/30 ,  G06F13/1668

    Abstract: A memory device includes a memory array and processing logic, operatively coupled with the memory array, to perform operations including causing a data burst to be initiated by toggling a logical level of a control pin from a first level corresponding to a data burst inactive mode to a second level corresponding to a data burst active mode, wherein the data burst corresponds to a data transfer across an interface bus, causing the data burst to be suspended by toggling the logical level of the control pin from the second level to a third level corresponding to a data burst suspend mode, and causing the data burst to be resumed by toggling the logical level of the control pin from the third level to the second level.

    GANGED SINGLE LEVEL CELL VERIFY IN A MEMORY DEVICE
    107.
    发明申请
    GANGED SINGLE LEVEL CELL VERIFY IN A MEMORY DEVICE 有权

    公开(公告)号：US20230070208A1

    公开(公告)日：2023-03-09

    申请号：US17683153

    申请日：2022-02-28

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee ,  Tomoko Ogura Iwasaki

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/08 ,  G11C16/24

    Abstract: Control logic in a memory device identifies a set of memory cells in a block of a memory array, wherein the set of memory cells comprises two or more memory cells programmed during a program phase of a program operation and associated with a selected wordline of the memory array. The control logic further causes a program verify voltage to be applied to the selected wordline during a program verify phase of the program operation and performs concurrent sensing operations on the set of memory cells to determine whether each memory cell in the set of memory cells was programmed to at least the program verify voltage during the program phase of the program operation.

    SACRIFICIAL STRINGS IN A MEMORY DEVICE TO DETECT READ DISTURB
    108.
    发明申请
    SACRIFICIAL STRINGS IN A MEMORY DEVICE TO DETECT READ DISTURB 有权

    公开(公告)号：US20230060440A1

    公开(公告)日：2023-03-02

    申请号：US17877411

    申请日：2022-07-29

    Applicant: Micron Technology, Inc.

    Inventor： Kishore Kumar Muchherla ,  Violante Moschiano ,  Akira Goda ,  Jeffrey S. McNeil ,  Eric N. Lee

    IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/406 ,  G11C11/4072

    Abstract: Control logic in a memory device determines to initiate a string read operation on a first memory string of a plurality of memory strings in a block of a memory array of the memory device, the block comprising a plurality of wordlines, wherein each of the plurality of memory strings comprises a plurality of memory cells associated with the plurality of wordlines, and wherein the first memory string is designated as a sacrificial string. The control logic further causes a read voltage to be applied to each of the plurality of wordlines of the memory array concurrently and senses a level of current flowing through the first memory string designated as the sacrificial string while the read voltage is applied to each of the plurality of wordline. In addition, the control logic identifies, based on the level of current flowing through the first memory string designated as the sacrificial string, whether a threshold level of read disturb has occurred on the block.

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