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    Memory cells, methods of forming memory cells and methods of forming memory arrays
    101.
    发明授权
    Memory cells, methods of forming memory cells and methods of forming memory arrays 有权
    存储单元，形成存储单元的方法和形成存储器阵列的方法

    公开(公告)号：US09166156B2

    公开(公告)日：2015-10-20

    申请号：US14251421

    申请日：2014-04-11

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  John K. Zahurak

    IPC: H01L29/02 ,  H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/06 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1683

    Abstract: Some embodiments include memory cells which have multiple programmable material structures between a pair of electrodes. One of the programmable material structures has a first edge, and another of the programmable material structures has a second edge that contacts the first edge. Some embodiments include methods of forming an array of memory cells. First programmable material segments are formed over bottom electrodes. The first programmable material segments extend along a first axis. Lines of second programmable material are formed over the first programmable material segments, and are formed to extend along a second axis that intersects the first axis. The second programmable material lines have lower surfaces that contact upper surfaces of the first programmable material segments. Top electrode lines are formed over the second programmable material lines.

    Abstract translation: 一些实施例包括在一对电极之间具有多个可编程材料结构的存储器单元。 可编程材料结构之一具有第一边缘，另一个可编程材料结构具有接触第一边缘的第二边缘。 一些实施例包括形成存储器单元阵列的方法。 第一可编程材料段形成在底部电极上。 第一可编程材料段沿第一轴线延伸。 第二可编程材料的线形成在第一可编程材料段上，并且形成为沿与第一轴相交的第二轴线延伸。 第二可编程材料线具有接触第一可编程材料段的上表面的下表面。 顶部电极线形成在第二可编程材料线上。

    CONFINED CELL STRUCTURES AND METHODS OF FORMING CONFINED CELL STRUCTURES
    102.
    发明申请
    CONFINED CELL STRUCTURES AND METHODS OF FORMING CONFINED CELL STRUCTURES 审中-公开
    确定的细胞结构和形成限制性细胞结构的方法

    公开(公告)号：US20150287909A1

    公开(公告)日：2015-10-08

    申请号：US14746462

    申请日：2015-06-22

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Gurtej Sandhu

    IPC: H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  H01L43/02 ,  H01L43/10

    CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

    Abstract: Techniques for reducing damage in memory cells are provided. Memory cell structures are typically formed using dry etch and/or planarization processes which damage certain regions of the memory cell structure. In one or more embodiments, certain regions of the cell structure may be sensitive to damage. For example, the free magnetic region in magnetic memory cell structures may be susceptible to demagnetization. Such regions may be substantially confined by barrier materials during the formation of the memory cell structure, such that the edges of such regions are protected from damaging processes. Furthermore, in some embodiments, a memory cell structure is formed and confined within a recess in dielectric material.

    Abstract translation: 提供了减少存储单元损坏的技术。 通常使用破坏存储单元结构的某些区域的干蚀刻和/或平坦化处理来形成存储单元结构。 在一个或多个实施例中，细胞结构的某些区域可能对损伤敏感。 例如，磁存储单元结构中的自由磁区可能易于退磁。 这样的区域在形成存储单元结构期间可以基本上被阻挡材料限制，使得这些区域的边缘被保护免受损坏的过程。 此外，在一些实施例中，存储单元结构形成并限制在电介质材料的凹部内。

    MEMORY DEVICES INCLUDING PHASE CHANGE MATERIAL ELEMENTS
    106.
    发明申请
    MEMORY DEVICES INCLUDING PHASE CHANGE MATERIAL ELEMENTS 有权
    包含相变材料元素的存储器件

    公开(公告)号：US20150155481A1

    公开(公告)日：2015-06-04

    申请号：US14615659

    申请日：2015-02-06

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/06 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675 ,  H01L45/1683

    Abstract: Memory devices having a plurality of memory cells, with each memory cell including a phase change material having a laterally constricted portion thereof. The laterally constricted portions of adjacent memory cells are vertically offset and positioned on opposite sides of the memory device. Also disclosed are memory devices having a plurality of memory cells, with each memory cell including first and second electrodes having different widths. Adjacent memory cells have the first and second electrodes offset on vertically opposing sides of the memory device. Methods of forming the memory devices are also disclosed.

    Abstract translation: 具有多个存储单元的存储器件，每个存储单元包括具有横向收缩部分的相变材料。 相邻存储单元的横向收缩部分垂直偏移并且位于存储器件的相对侧上。 还公开了具有多个存储单元的存储器件，每个存储器单元包括具有不同宽度的第一和第二电极。 相邻存储器单元具有在存储器件的垂直相对侧上偏移的第一和第二电极。 还公开了形成存储器件的方法。

    STT-MRAM CELL STRUCTURES
    107.
    发明申请
    STT-MRAM CELL STRUCTURES 有权
    STT-MRAM细胞结构

    公开(公告)号：US20150125966A1

    公开(公告)日：2015-05-07

    申请号：US14595955

    申请日：2015-01-13

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Gurtej Sandhu

    IPC: H01L43/12

    CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  H01L29/66007 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

    Abstract: A magnetic cell structure including a nonmagnetic bridge, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, and a nonmagnetic bridge electrically connecting the free layer and the pinned layer. The shape and/or configuration of the nonmagnetic bridge directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer of the structure is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell.

    Abstract translation: 提供包括非磁性桥的磁性单元结构以及制造该结构的方法。 磁性电池结构包括自由层，钉扎层和电连接自由层和钉扎层的非磁性桥。 非磁性桥的形状和/或构造使编程电流通过磁性单元结构，使得结构自由层中编程电流的横截面面积小于结构的横截面。 自由层中编程电流的横截面积的减小使编程电流能够达到自由层中的关键开关电流密度并切换自由层的磁化，对磁性单元进行编程。

    Vertical transistor phase change memory
    108.
    发明授权
    Vertical transistor phase change memory 有权
    垂直晶体管相变存储器

    公开(公告)号：US09024290B2

    公开(公告)日：2015-05-05

    申请号：US14445669

    申请日：2014-07-29

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L27/249 ,  G11C13/0004 ,  H01L27/2454 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/124 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1691

    Abstract: Vertical transistor phase change memory and methods of processing phase change memory are described herein. One or more methods include forming a dielectric on at least a portion of a vertical transistor, forming an electrode on the dielectric, and forming a vertical strip of phase change material on a portion of a side of the electrode and on a portion of a side of the dielectric extending along the electrode and the dielectric into contact with the vertical transistor.

    Abstract translation: 本文描述了垂直晶体管相变存储器和处理相变存储器的方法。 一种或多种方法包括在垂直晶体管的至少一部分上形成电介质，在电介质上形成电极，并且在电极侧面的一部分和侧面的一部分上形成垂直条状的相变材料 的电介质沿着电极延伸并且电介质与垂直晶体管接触。

    Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells
    110.
    发明授权
    Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells 有权
    非易失性存储单元的阵列和形成非易失性存储单元阵列的方法

    公开(公告)号：US08854863B2

    公开(公告)日：2014-10-07

    申请号：US13970369

    申请日：2013-08-19

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu

    IPC: G11C11/00 ,  H01L45/00 ,  G11C5/02 ,  G11C5/06 ,  H01L21/302 ,  H01L27/24 ,  H01L27/102

    CPC classification number: H01L45/1608 ,  G11C5/02 ,  G11C5/06 ,  G11C13/0004 ,  G11C2213/71 ,  H01L21/302 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/165

    Abstract: An array of nonvolatile memory cells includes a plurality of vertically stacked tiers of nonvolatile memory cells. The tiers individually include a first plurality of horizontally oriented first electrode lines and a second plurality of horizontally oriented second electrode lines crossing relative to the first electrode lines. Individual of the memory cells include a crossing one of the first electrode lines and one of the second electrode lines and material there-between. Specifically, programmable material, a select device in series with the programmable material, and current conductive material in series between and with the programmable material and the select device are provided in series with such crossing ones of the first and second electrode lines. The material and devices may be oriented for predominant current flow in defined horizontal and vertical directions. Method and other implementations and aspects are disclosed.

    Abstract translation: 非易失性存储单元的阵列包括多个垂直堆叠的非易失性存储单元层。 层分别包括第一多个水平取向的第一电极线和相对于第一电极线交叉的第二多个水平取向的第二电极线。 存储单元的个体包括第一电极线和第二电极线中的一个之间的交叉的一个以及其间的材料。 具体地说，与可编程材料串联的选择装置以及与可编程材料和选择装置之间串联的当前导电材料与第一和第二电极线中交叉的那些串联地提供。 材料和装置可以被定向成在限定的水平和垂直方向上的主要电流流动。 公开了方法和其他实现和方面。

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