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    FLASH MEMORY SYSTEM AND FLASH MEMORY DEVICE THEREOF
    101.
    发明申请
    FLASH MEMORY SYSTEM AND FLASH MEMORY DEVICE THEREOF 有权

    公开(公告)号：US20220188238A1

    公开(公告)日：2022-06-16

    申请号：US17118239

    申请日：2020-12-10

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Chun-Lien Su ,  Chun-Hsiung Hung ,  Shuo-Nan Hung

    IPC: G06F12/0882 ,  G06F12/0862 ,  G06F12/02 ,  G06F11/10

    Abstract: A flash memory system and a flash memory thereof are provided. The flash memory device includes a NAND flash memory and a control circuit. The NAND flash memory chip includes a cache memory, a page buffer; and an NAND flash memory array. The NAND flash memory array includes a plurality of pages, wherein each page includes a plurality of sub-pages, each sub-page has a sub-page length. The cache memory is composed of a plurality of sub cache and each sub cache corresponds to different pages of the NAND flash memory array. The page buffer is composed of a plurality of sub-page buffers and each sub-page buffer corresponds to different pages of the NAND flash memory array. The control circuit is coupled to the host and the NAND flash memory, and performs an access operation in units of one sub-page.

    MULTI-DIE MEMORY APPARATUS AND IDENTIFICATION METHOD THEREOF
    102.
    发明申请
    MULTI-DIE MEMORY APPARATUS AND IDENTIFICATION METHOD THEREOF 有权

    公开(公告)号：US20210349645A1

    公开(公告)日：2021-11-11

    申请号：US16870848

    申请日：2020-05-08

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Chun-Hsiung Hung ,  Su-Chueh Lo

    IPC: G06F3/06 ,  H01L25/065

    Abstract: A multi-die memory apparatus and identification method thereof are provided. The identification method includes: sending an identification initial command and a first start command to a plurality of memory devices by a controller for starting a first identification period; respectively generating a plurality of first target numbers by the memory devices; respectively performing first counting actions and comparing a plurality of first counting numbers with the first target numbers by a plurality of un-identified memory devices to set a first time-up memory device of the memory devices; and, setting an identification code of the first time-up memory device of the un-identified memory devices to be a first value.

    Fast page continuous read
    103.
    发明授权
    Fast page continuous read 有权

    公开(公告)号：US10977121B2

    公开(公告)日：2021-04-13

    申请号：US16533463

    申请日：2019-08-06

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Shuo-Nan Hung ,  Chun-Hsiung Hung

    IPC: G06F11/10 ,  H03M13/15 ,  G11C11/4093 ,  G11C11/4094

    Abstract: A memory device such as a page mode NAND flash is operated, using a first pipeline stage, to clear a page buffer to a second buffer level, and transfer a page to the page buffer; a second pipeline stage to clear the second buffer level to the third buffer level and transfer the page from the page buffer to the second buffer level; a third pipeline stage to move the page to the third buffer level and execute in an interleaved fashion a first ECC function over data in a first part of the page and output the first part of the page while performing an second ECC function, and to execute the first ECC function over data in a second part of the page in the third buffer level, and to output the second part while performing the second ECC function.

    Non-volatile memory with physical unclonable function and random number generator
    104.
    发明授权
    Non-volatile memory with physical unclonable function and random number generator 有权

    公开(公告)号：US10855477B2

    公开(公告)日：2020-12-01

    申请号：US15857341

    申请日：2017-12-28

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Shih-Chang Huang

    IPC: G06F11/30 ,  H04L9/32 ,  H04L9/08 ,  G09C1/00

    Abstract: A device which can be implemented on a single packaged integrated circuit or a multichip includes a plurality of non-volatile memory cells, and logic to use a physical unclonable function to produce an initial key and to store the initial key in a set of non-volatile memory cells in the plurality of non-volatile memory cells. The device can include logic to use a random number generator to generate a random number, and logic to combine the initial key and the random number to produce an enhanced key. The physical unclonable function can use entropy derived from non-volatile memory cells in the plurality of non-volatile memory cells to produce the initial key. Logic is described to disable changes to data in the set of non-volatile memory cells, and thereby freeze the key after it is stored in the set.

    Low latency memory erase suspend operation
    105.
    发明授权
    Low latency memory erase suspend operation 有权

    公开(公告)号：US10825529B2

    公开(公告)日：2020-11-03

    申请号：US14455749

    申请日：2014-08-08

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Wen-Ming Hsu ,  Nai-Ping Kuo ,  Chun-Hsiung Hung

    IPC: G11C16/34 ,  G11C16/16

    Abstract: A method for an erase operation on a nonvolatile memory array with low-latency erase suspend is described. The nonvolatile memory array includes a plurality of blocks of memory cells, each block including a plurality of sectors of memory cells. The method includes, in response to an erase command identifying a block in the plurality of blocks in the array, erasing the plurality of sectors in the identified block, and determining whether there are over-erased cells in each sector. The method includes recording the over-erased cells for the sector. The method also includes responsive to suspend before a soft program pulse for the sector, applying a correction pulse to the recorded cells.

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