公开(公告)号：US20070254419A1

公开(公告)日：2007-11-01

申请号：US11819198

申请日：2007-06-26

申请人： Atsuhiko Kanda ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto ,  Yutaka Hirose ,  Tomohiro Murata

发明人： Atsuhiko Kanda ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto ,  Yutaka Hirose ,  Tomohiro Murata

IPC分类号： H01L21/338

CPC分类号： H01L29/7787 ,  H01L27/14609 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/14656 ,  H01L29/2003 ,  H01L29/66462

摘要： A semiconductor device has a first nitride semiconductor layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer and having such a composition as to generate a 2-dimensional electron gas layer in the upper portion of the first nitride semiconductor layer, and an electrode having an ohmic property and formed selectively on the second nitride semiconductor layer. The second nitride semiconductor layer includes a contact area having at least one inclined portion with a bottom or wall surface thereof being inclined toward the upper surface of the first nitride semiconductor layer and defining a depressed cross-sectional configuration. The electrode is formed on the contact area.

公开(公告)号：US20070176215A1

公开(公告)日：2007-08-02

申请号：US11600102

申请日：2006-11-16

申请人： Manabu Yanagihara ,  Masahiro Hikita ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

发明人： Manabu Yanagihara ,  Masahiro Hikita ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC分类号： H01L29/76

CPC分类号： H01L29/7787 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/432 ,  H01L29/66462

摘要： A transistor includes a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer and has a band gap larger than that of the first semiconductor layer, a control layer formed on the second semiconductor layer and contains p-type impurities, a gate electrode formed in contact with at least part of the control layer and a source electrode and a drain electrode formed on both sides of the control layer, respectively. A third semiconductor layer made of material having a lower etch rate than that of the control layer is formed between the control layer and the second semiconductor layer.

摘要翻译： 晶体管包括形成在基板上的第一半导体层，形成在第一半导体层上并具有比第一半导体层的带隙大的带隙的第二半导体层，形成在第二半导体层上并包含p型 杂质，形成为与控制层的至少一部分接触的栅极电极以及分别形成在控制层两侧的源电极和漏电极。 在控制层和第二半导体层之间形成由蚀刻率低于控制层的材料制成的第三半导体层。

公开(公告)号：US07241703B2

公开(公告)日：2007-07-10

申请号：US10855328

申请日：2004-05-28

申请人： Masahiro Hikita ,  Yasuhiro Uemoto

发明人： Masahiro Hikita ,  Yasuhiro Uemoto

IPC分类号： H01L21/31

CPC分类号： C23C16/45523 ,  C23C16/402 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/31612 ,  H01L21/76834 ,  H01L21/76837

摘要： A method of forming films in a semiconductor device that can appropriately control a resistance value of a thin film resistance on an ozone TEOS film while preventing a metal thin film from remaining around a surface step unit after the metal thin film was dry etched. First, as shown in FIG. 1A, a step unit with the height of about 1 μm is formed by forming elements such as HBT on a semiconductor substrate made up of semi-insulating GaAs. Next, as shown in FIG. 1B, a first ozone TEOS film with the thickness of 900 nm by a Normal pressure CVD method using mixed gas of tetraethoxysilane with ozone. Then, a second ozone TEOS film with the thickness of 100 nm is formed by reducing the ozone concentration to 10 g/m3, while maintaining the substrate temperature at 350° C.

摘要翻译： 在半导体器件中形成薄膜的方法，其可以在金属薄膜被干蚀刻之后防止金属薄膜残留在表面台阶单元周围，从而适当地控制臭氧TEOS薄膜上的薄膜电阻的电阻值。 首先，如图1所示。 在图1A中，通过在由半绝缘GaAs构成的半导体衬底上形成诸如HBT的元件来形成高度约为1um的台阶单元。 接下来，如图3所示。 1B，使用四乙氧基硅烷与臭氧的混合气体，通过常压CVD法形成厚度为900nm的第一臭氧TEOS膜。 然后，通过将臭氧浓度降低至10g / m 3，同时将基板温度保持在350℃，形成厚度为100nm的第二臭氧TEOS膜。

公开(公告)号：US07238970B2

公开(公告)日：2007-07-03

申请号：US10971098

申请日：2004-10-25

申请人： Yutaka Hirose ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto

发明人： Yutaka Hirose ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto

IPC分类号： H01L29/732

CPC分类号： H01L21/28575 ,  C30B25/02 ,  C30B29/40 ,  H01L29/2003 ,  H01L29/452 ,  H01L29/802 ,  H01L33/32 ,  H01L33/40

摘要： A semiconductor device of the present invention comprises a Group III-V nitride semiconductor layer of gallium nitride or the like having n-type conductivity and at least one ohmic electrode formed on the Group III-V nitride semiconductor layer of gallium nitride or the like having n-type conductivity. The ohmic electrode is formed of a conductive material containing a metal boride.

摘要翻译： 本发明的半导体器件包括具有n型导电性的氮化镓等的III-V族氮化物半导体层和形成在氮化镓等的III-V族氮化物半导体层上的至少一个欧姆电极， n型电导率。 欧姆电极由含有金属硼化物的导电材料形成。

公开(公告)号：US20060108605A1

公开(公告)日：2006-05-25

申请号：US11271833

申请日：2005-11-14

申请人： Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda

发明人： Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC分类号： H01L29/739

CPC分类号： H01L29/66143 ,  H01L29/872

摘要： A Schottky barrier diode includes a first semiconductor layer and a second semiconductor layer successively formed above a substrate; and a high-resistance region formed in the first semiconductor layer and the second semiconductor layer and having higher resistance than the first semiconductor layer and the second semiconductor layer. A Schottky electrode and an ohmic electrode spaced from each other are formed on the second semiconductor layer in a portion surrounded with the high-resistance region.

摘要翻译： 肖特基势垒二极管包括依次形成在衬底上的第一半导体层和第二半导体层; 以及形成在第一半导体层和第二半导体层中并且具有比第一半导体层和第二半导体层更高的电阻的高电阻区域。 彼此间隔开的肖特基电极和欧姆电极在被高电阻区域包围的部分中形成在第二半导体层上。

公开(公告)号：US20050082568A1

公开(公告)日：2005-04-21

申请号：US10862452

申请日：2004-06-08

申请人： Yutaka Hirose ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto ,  Tomohiro Murata

发明人： Yutaka Hirose ,  Daisuke Ueda ,  Tsuyoshi Tanaka ,  Yasuhiro Uemoto ,  Tomohiro Murata

IPC分类号： H01L21/28 ,  H01L21/338 ,  H01L29/20 ,  H01L29/417 ,  H01L29/778 ,  H01L29/812 ,  H01L31/0328

CPC分类号： H01L29/7787 ,  H01L29/2003

摘要： A semiconductor device has a sapphire substrate, a semiconductor layer made of GaN provided on the sapphire substrate, a multilayer film provided on the semiconductor layer, and an electrode in ohmic contact with the multilayer film. The multilayer film has been formed by alternately stacking two types of semiconductor layers having different amounts of piezopolarization or different amounts of spontaneous polarization and each containing an n-type impurity so that electrons are induced at the interface between the two types of semiconductor layers. This allows the contact resistance between the electrode and the multilayer film and a parasitic resistance in a current transmission path to be reduced to values lower than in a conventional semiconductor device.

摘要翻译： 半导体器件具有蓝宝石衬底，设置在蓝宝石衬底上的由GaN制成的半导体层，设置在半导体层上的多层膜和与该多层膜欧姆接触的电极。 已经通过交替地堆叠具有不同量的极化或不同量的自发极化的两种类型的半导体层，并且每个含有n型杂质，以便在两种类型的半导体层之间的界面处诱导电子而形成多层膜。 这允许电极和多层膜之间的接触电阻和电流传输路径中的寄生电阻降低到比常规半导体器件中的值更低的值。

公开(公告)号：US20050001235A1

公开(公告)日：2005-01-06

申请号：US10834362

申请日：2004-04-29

申请人： Tomohiro Murata ,  Yutaka Hirose ,  Yoshito Ikeda ,  Tsuyoshi Tanaka ,  Kaoru Inoue ,  Daisuke Ueda ,  Yasuhiro Uemoto

发明人： Tomohiro Murata ,  Yutaka Hirose ,  Yoshito Ikeda ,  Tsuyoshi Tanaka ,  Kaoru Inoue ,  Daisuke Ueda ,  Yasuhiro Uemoto

IPC分类号： H01L21/20 ,  H01L21/28 ,  H01L21/338 ,  H01L29/20 ,  H01L29/417 ,  H01L29/778 ,  H01L29/812 ,  H01L31/0328 ,  H01S5/30

CPC分类号： H01L29/7787 ,  H01L21/02425 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41766

摘要： A semiconductor device has: a buffer layer formed on a conductive substrate and made of AlxGa1-xN with a high resistance; an element-forming layer formed on the buffer layer, having a channel layer, and made of undoped GaN and N-type AlyGa1-yN; and a source electrode, a drain electrode and a gate electrode which are selectively formed on the element-forming layer. The source electrode is filled in a through hole provided in the buffer layer and the element-forming layer, and is thus electrically connected to the conductive substrate.

摘要翻译： 半导体器件具有：形成在导电基板上并由高电阻的Al x Ga 1-x N构成的缓冲层; 形成在缓冲层上的元件形成层，具有沟道层，由未掺杂的GaN和N型Al y Ga 1-y N制成; 以及选择性地形成在元件形成层上的源电极，漏电极和栅电极。 源电极被填充在设置在缓冲层和元件形成层中的通孔中，因此电连接到导电基板。

公开(公告)号：US08779438B2

公开(公告)日：2014-07-15

申请号：US13569014

申请日：2012-08-07

申请人： Masahiro Hikita ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

发明人： Masahiro Hikita ,  Tetsuzo Ueda ,  Manabu Yanagihara ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka

IPC分类号： H01L29/15 ,  H01L31/0256 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

CPC分类号： H01L29/7786 ,  H01L29/0843 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/7783

摘要： An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.

摘要翻译： 依次形成AlN缓冲层，未掺杂的GaN层，未掺杂的AlGaN层，p型GaN层和重掺杂的p型GaN层。 栅电极与重掺杂的p型GaN层形成欧姆接触。 源电极和漏电极设置在未掺杂的AlGaN层上。 通过在未掺杂的AlGaN层和未掺杂的GaN层和p型GaN层之间的界面处产生的二维电子气在栅极区域中形成pn结，从而可以提高栅极电压。

公开(公告)号：US08742467B2

公开(公告)日：2014-06-03

申请号：US13613724

申请日：2012-09-13

申请人： Tatsuo Morita ,  Daisuke Ueda ,  Yasuhiro Uemoto ,  Tetsuzo Ueda

发明人： Tatsuo Morita ,  Daisuke Ueda ,  Yasuhiro Uemoto ,  Tetsuzo Ueda

IPC分类号： H01L29/772 ,  H01L29/778

CPC分类号： H01L29/7787 ,  H01L27/0605 ,  H01L29/1066 ,  H01L29/2003

摘要： A bidirectional switching device includes a semiconductor multilayer structure made of a nitride semiconductor, a first ohmic electrode and a second ohmic electrode which are formed on the semiconductor multilayer structure, and a first gate electrode and a second gate electrode. The first gate electrode is covered with a first shield electrode having a potential substantially equal to that of the first ohmic electrode. The second gate electrode is covered with the second shield electrode having a potential substantially equal to that of the second ohmic electrode. An end of the first shield electrode is positioned between the first gate electrode and the second gate electrode, and an end of the second shield electrode is positioned between the second gate electrode and the first gate electrode.

摘要翻译： 双向开关器件包括由半导体多层结构上形成的由氮化物半导体，第一欧姆电极和第二欧姆电极构成的半导体多层结构以及第一栅电极和第二栅电极。 第一栅电极被第一屏蔽电极覆盖，该第一屏蔽电极的电位基本上等于第一欧姆电极的电位。 第二栅电极被第二屏蔽电极覆盖，其电位基本上等于第二欧姆电极的电位。 第一屏蔽电极的端部位于第一栅极电极和第二栅极电极之间，第二屏蔽电极的端部位于第二栅极电极和第一栅极电极之间。

公开(公告)号：US08344423B2

公开(公告)日：2013-01-01

申请号：US13360275

申请日：2012-01-27

申请人： Yasuhiro Uemoto ,  Masahiro Hikita ,  Tetsuzo Ueda ,  Tsuyoshi Tanaka ,  Daisuke Ueda

发明人： Yasuhiro Uemoto ,  Masahiro Hikita ,  Tetsuzo Ueda ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC分类号： H01L29/66

CPC分类号： H01L29/7786 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/7783

摘要： A nitride semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider band gap than the first nitride semiconductor layer; and a third nitride semiconductor layer formed on the second nitride semiconductor layer. A region of the third nitride semiconductor layer located below the gate electrode is formed with a control region having a p-type conductivity, and a region of the third nitride semiconductor layer located between the gate electrode and each of the source electrode and the drain electrode is formed with a high resistive region having a higher resistance than the that of the control region.

摘要翻译： 氮化物半导体器件包括：第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更宽的带隙的第二氮化物半导体层; 以及形成在所述第二氮化物半导体层上的第三氮化物半导体层。 位于栅电极下方的第三氮化物半导体层的区域形成有具有p型导电性的控制区域，以及位于栅电极与源电极和漏极之间的第三氮化物半导体层的区域 形成有具有比控制区域更高的电阻的高电阻区域。