公开(公告)号：US20240074200A1

公开(公告)日：2024-02-29

申请号：US17821677

申请日：2022-08-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bing ZHOU ,  Senaka KANAKAMEDALA ,  Raghuveer S. MAKALA

IPC: H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: A first-tier alternating stack of first-tier insulating layers and first-tier sacrificial material layers is formed over a substrate. A first-tier memory opening is formed, and is filled with a first-tier sacrificial memory opening fill structure. A second-tier alternating stack of second-tier insulating layers and second-tier sacrificial material layers is formed. An etch mask layer is formed, and a second-tier memory opening is formed through the second-tier alternating stack. An etch mask removal process is performed which collaterally removes a top portion of the first-tier sacrificial memory opening fill structure. A sacrificial pillar structure is formed by performing a selective material deposition process. An inter-tier memory opening is formed by removing the first-tier sacrificial memory opening fill structure and at least a central portion of the sacrificial pillar structure. A memory opening fill structure is formed, and the sacrificial material layers are replaced with electrically conductive layers.

公开(公告)号：US20240064991A1

公开(公告)日：2024-02-22

申请号：US17820997

申请日：2022-08-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kartik SONDHI ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Tiffany SANTOS ,  Fei ZHOU ,  Joyeeta NAG ,  Bhagwati PRASAD ,  Adarsh RAJASHEKHAR

IPC: H01L27/11597 ,  H01L27/1159

CPC classification number: H01L27/11597 ,  H01L27/1159

Abstract: A semiconductor memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of discrete ferroelectric material portions and a vertical semiconductor channel. In one embodiment, the discrete ferroelectric material portions include a ferroelectric alloy material of a first dielectric metal oxide material and a second dielectric metal oxide material. In another embodiment, each of the discrete ferroelectric material portions is oxygen-deficient.

公开(公告)号：US20230420370A1

公开(公告)日：2023-12-28

申请号：US17808333

申请日：2022-06-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Kartik SONDHI

IPC: H01L23/532 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/53266 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located within the memory openings. Each of the memory opening fill structures includes a respective vertical semiconductor channel and a respective vertical stack of memory elements. Each of the electrically conductive layers include a molybdenum layer and a plurality of conductive capping material portions in contact with an outer sidewall of a respective one of the memory opening fill structures.

公开(公告)号：US20230354608A1

公开(公告)日：2023-11-02

申请号：US18344411

申请日：2023-06-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Noriyuki NAGAHATA ,  Masanori TSUTSUMI ,  Fei ZHOU ,  Raghuveer S. MAKALA

IPC: H10B43/27 ,  G11C16/04 ,  H10B43/10 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H01L21/768

CPC classification number: H10B43/27 ,  G11C16/0483 ,  H10B43/10 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H01L21/76843

Abstract: A method of forming a memory device includes forming an alternating stack of disposable material layers and silicon nitride layers over a substrate, forming a memory opening through the alternating stack, forming a memory film in the memory opening, forming a vertical semiconductor channel over the memory film in the memory opening, forming a backside trench through the alternating stack, forming laterally-extending cavities by removing the disposable material layers selective to the silicon nitride layers through the backside trench, oxidizing portions of the silicon nitride layers exposed in the laterally-extending cavities to form insulating layers, and replacing remaining portions of the silicon nitride layers with electrically conductive layers.

公开(公告)号：US20230345719A1

公开(公告)日：2023-10-26

申请号：US17659902

申请日：2022-04-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kartik SONDHI ,  Adarsh RAJASHEKHAR ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA

IPC: H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: An alternating stack of insulating layers and electrically conductive layers is formed over a substrate, and a memory opening vertically extends through the alternating stack. The memory opening is laterally expanded at levels of the insulating layers. At least one blocking dielectric layer is formed in the memory opening. A first vertical stack of discrete charge storage elements is formed at levels of the electrically conductive layers. A second vertical stack of discrete dielectric material portions is formed at the levels of the insulating layers. A tunneling dielectric layer is formed over the first vertical stack and the second vertical stack. A vertical semiconductor channel is formed on the tunneling dielectric layer.

公开(公告)号：US20230178425A1

公开(公告)日：2023-06-08

申请号：US18151662

申请日：2023-01-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Roshan Jayakhar TIRUKKONDA ,  Bing ZHOU ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Senaka KANAKAMEDALA ,  Adarsh RAJASHEKHAR

IPC: H01L21/768 ,  H01L21/306

CPC classification number: H01L21/76831 ,  H01L21/30608

Abstract: A method of forming a structure includes forming an alternating stack of first material layers and second material layers over a substrate, forming a first etch mask material layer, forming a first cladding liner, and forming a via opening through the alternating stack by performing an anisotropic etch process that employs a combination of at least the first cladding liner and the first etch mask material layer as a composite etch mask structure.

公开(公告)号：US20230018394A1

公开(公告)日：2023-01-19

申请号：US17378196

申请日：2021-07-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. MAKALA ,  Senaka KANAKAMEDALA ,  Rahul SHARANGPANI ,  Ramy Nashed Bassely SAID

IPC: H01L27/1157 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/06

Abstract: A three-dimensional memory device includes a vertical repetition of multiple instances of a unit layer stack. The unit layer stack includes, in order, an airgap-containing insulating layer, a first interfacial dielectric capping layer, a metal layer, and a second interfacial dielectric capping layer. Memory stack structures extend through the vertical repetition. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements located at levels of the metal layers.

公开(公告)号：US20220285386A1

公开(公告)日：2022-09-08

申请号：US17192463

申请日：2021-03-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely SAID ,  Raghuveer S. MAKALA ,  Senaka KANAKAMEDALA ,  Fei ZHOU

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack and having lateral protrusions at levels of the electrically conductive layers, and memory opening fill structures located in the memory openings. Each of the memory opening fill structures includes a vertical semiconductor channel, a dielectric material liner laterally surrounding the vertical semiconductor channel, and a vertical stack of discrete memory elements laterally surrounding the dielectric material liner and located within volumes of the lateral protrusions. Each discrete memory element includes a vertical inner sidewall and a convex or stepped outer sidewall.

公开(公告)号：US20220254797A1

公开(公告)日：2022-08-11

申请号：US17169987

申请日：2021-02-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely SAID ,  Jiahui YUAN ,  Senaka KANAKAMEDALA ,  Raghuveer S. MAKALA ,  Dana LEE

IPC: H01L27/11556 ,  H01L29/66 ,  H01L29/423 ,  H01L29/788

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric layer, and a vertical stack of memory elements located at levels of the electrically conductive layers between a respective vertically neighboring pair of the insulating layers. Each of the memory elements includes a first memory material portion, and a second memory material portion that is vertically spaced from and is electrically isolated from the first memory material portion by at least one blocking dielectric material portion.

公开(公告)号：US20220231048A1

公开(公告)日：2022-07-21

申请号：US17150561

申请日：2021-01-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Adarsh RAJASHEKHAR

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/1159

Abstract: A ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and containing a vertical stack of memory elements and a vertical semiconductor channel. Each memory element within the vertical stack of memory elements includes a crystalline ferroelectric memory material portion and an epitaxial template portion.