公开(公告)号：US20210043683A1

公开(公告)日：2021-02-11

申请号：US16531482

申请日：2019-08-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine H. Chiang ,  Chung-Te Lin ,  Mauricio Manfrini

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/02 ,  H01L43/12

Abstract: In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit has a magnetic tunnel junction (MTJ) device disposed within a dielectric structure over a substrate. The MTJ device has a MTJ disposed between a first electrode and a second electrode. A first unipolar selector is disposed within the dielectric structure and is coupled to the first electrode. The first unipolar selector is configured to allow current to flow through the MTJ device along a first direction. A second unipolar selector is disposed within the dielectric structure and is coupled to the first electrode. The second unipolar selector is configured to allow current to flow through the MTJ device along a second direction opposite the first direction.

公开(公告)号：US10903239B2

公开(公告)日：2021-01-26

申请号：US16045058

申请日：2018-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-yuan Chang ,  Chun-Chen Chen ,  Po-Hsiang Huang ,  Lee-Chung Lu ,  Chung-Te Lin ,  Jerry Chang Jui Kao ,  Sheng-Hsiung Chen ,  Chin-Chou Liu

IPC: H01L27/118 ,  G06F30/398 ,  H01L27/02

Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.

公开(公告)号：US20200327274A1

公开(公告)日：2020-10-15

申请号：US16912229

申请日：2020-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Hsiung CHEN ,  Chung-Te Lin ,  Fong-Yuan Chang ,  Ho Che Yu ,  Li-Chun Tien

IPC: G06F30/398 ,  H01L27/02 ,  H01L27/118 ,  G06F30/394

Abstract: Placement methods described in this disclosure provide placement and routing rules where a system implementing the automatic placement and routing (APR) method arranges standard cell structures in a vertical direction that is perpendicular to the fins but parallel to the cell height. Layout methods described in this disclosure also improve device density and further reduce cell height by incorporating vertical power supply lines into standard cell structures. Pin connections can be used to electrically connect the power supply lines to standard cell structures, thus improving device density and performance. The APR process is also configured to rotate standard cells to optimize device layout.

公开(公告)号：US20200006423A1

公开(公告)日：2020-01-02

申请号：US16270484

申请日：2019-02-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Te Lin ,  Yen-Chung Ho ,  Pin-Cheng Hsu ,  Han-Ting Tsai ,  Katherine Chiang

IPC: H01L27/22 ,  H01L43/02 ,  G11C11/16 ,  H01L43/12 ,  G06F3/06

Abstract: An embodiment of an integrated circuit chip includes a combination processing core and magnetoresistive random access memory (MRAM) circuitry integrated into the chip. The MRAM circuitry includes a plurality of MRAM cells. The MRAM cells are organized into a number of memories, including a cache memory, a main or working memory and an optional secondary storage memory. The cache memory includes multiple cache levels.

公开(公告)号：US10276794B1

公开(公告)日：2019-04-30

申请号：US15799416

申请日：2017-10-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen Peng ,  Hui-Hsien Wei ,  Wei-Chih Wen ,  Pin-Ren Dai ,  Chien-Min Lee ,  Han-Ting Tsai ,  Jyu-Horng Shieh ,  Chung-Te Lin

IPC: H01L45/00 ,  H01L43/02 ,  H01L27/24

Abstract: A memory device includes a substrate, an etch stop layer, a protective layer, and a resistance switching element. The substrate has a memory region and a logic region, and includes a metallization pattern therein. The etch stop layer is over the substrate, and has a first portion over the memory region and a second portion over the logic region. The protective layer covers the first portion of the etch stop layer. The protective layer does not cover the second portion of the etch stop layer. The resistance switching element is over the memory region, and the resistance switching element is electrically connected to the metallization pattern through the etch stop layer and the protective layer.

公开(公告)号：US12200940B2

公开(公告)日：2025-01-14

申请号：US17874815

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Jong Chia ,  Chung-Te Lin ,  Feng-Cheng Yang ,  Meng-Han Lin ,  Sheng-Chen Wang

IPC: H10B51/20 ,  G11C11/22 ,  G11C11/56 ,  H01L29/66 ,  H01L29/78 ,  H10B51/10 ,  H10B51/30 ,  H01L21/28

Abstract: In an embodiment, a device includes: a first dielectric layer over a substrate; a word line over the first dielectric layer, the word line including a first main layer and a first glue layer, the first glue layer extending along a bottom surface, a top surface, and a first sidewall of the first main layer; a second dielectric layer over the word line; a first bit line extending through the second dielectric layer and the first dielectric layer; and a data storage strip disposed between the first bit line and the word line, the data storage strip extending along a second sidewall of the word line.

公开(公告)号：US12167608B2

公开(公告)日：2024-12-10

申请号：US17981608

申请日：2022-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H10B51/20 ,  G11C11/22 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78 ,  H10B43/20 ,  H10B43/27 ,  H10B51/10 ,  H10B51/30

Abstract: In an embodiment, a device includes: a source line extending in a first direction; a bit line extending in the first direction; a back gate between the source line and the bit line, the back gate extending in the first direction; a channel layer surrounding the back gate; a word line extending in a second direction, the second direction perpendicular to the first direction; and a data storage layer extending along the word line, the data storage layer between the word line and the channel layer, the data storage layer between the word line and the bit line, the data storage layer between the word line and the source line.

公开(公告)号：US20240397724A1

公开(公告)日：2024-11-28

申请号：US18786864

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chih Lai ,  Chung-Te Lin

IPC: H10B43/40 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/51 ,  H10B43/27

Abstract: A semiconductor device and method of forming thereof that includes a transistor of a peripheral circuit on a substrate. A first interconnect structure such as a first access line is formed over the transistor. A via extends above the first access line. A plurality of memory cell structures is formed over the interconnect structure and the via. A second interconnect structure, such as a second access line, is formed over the memory cell structure. The first access line is coupled to a first memory cell of the plurality of memory cell structures and second access line is coupled to a second memory cell of the plurality of memory cell structures.

公开(公告)号：US20240312830A1

公开(公告)日：2024-09-19

申请号：US18673571

申请日：2024-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Jong Chia ,  Meng-Han Lin ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Chung-Te Lin

IPC: H01L21/762 ,  G11C7/18 ,  H10B51/20 ,  H10B99/00

CPC classification number: H01L21/76237 ,  G11C7/18 ,  H10B51/20 ,  H10B99/00

Abstract: A method of forming a three-dimensional (3D) memory device includes: forming a layer stack over a substrate, the layer stack including alternating layers of a first dielectric material and a second dielectric material; forming trenches extending through the layer stack; replacing the second dielectric material with an electrically conductive material to form word lines (WLs); lining sidewalls and bottoms of the trenches with a ferroelectric material; filling the trenches with a third dielectric material; forming bit lines (BLs) and source lines (SLs) extending vertically through the third dielectric material; removing portions of the third dielectric material to form openings in the third dielectric material between the BLs and the SLs; forming a channel material along sidewalls of the openings; and filling the openings with a fourth dielectric.

公开(公告)号：US20240203997A1

公开(公告)日：2024-06-20

申请号：US18595049

申请日：2024-03-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-yuan Chang ,  Chun-Chen Chen ,  Po-Hsiang Huang ,  Lee-Chung Lu ,  Chung-Te Lin ,  Jerry Chang Jui Kao ,  Sheng-Hsiung Chen ,  Chin-Chou Liu

IPC: H01L27/118 ,  G06F30/398 ,  H01L27/02

CPC classification number: H01L27/11807 ,  G06F30/398 ,  H01L27/0207 ,  H01L2027/11862 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2027/11881 ,  H01L2027/11885

Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.