公开(公告)号：US20010015656A1

公开(公告)日：2001-08-23

申请号：US09790050

申请日：2001-02-21

发明人： Nobuaki Tsuji

IPC分类号： H03K019/02

CPC分类号： H03K19/018592

摘要： A buffer circuit comprises a data input terminal; an enabling terminal inputting an enabling signal; an output terminal; a first power source terminal supplying high potential voltage; a second power source terminal supplying low potential voltage; a first N-channel transistor connected between said output terminal and said second power source terminal; a common bulk P-channel transistors group of a first to fifth transistors formed on a common bulk region; a second N-channel transistor formed between said one node and said second power source terminal and comprising a gate electrode supplied an inverted signal of an enabling signal; and a logic circuit either inputting an inverted signal of said input signal to said gate electrodes of said first P-channel transistor and said first N-channel transistor, or inputting a signal keeping said first P-channel transistor turned off to the gate electrode of said first P-channel according to state of said enabling signal.

摘要翻译： 缓冲电路包括数据输入端; 使能终端输入使能信号; 输出端子; 提供高电位电压的第一电源端子; 提供低电位电压的第二电源端子; 连接在所述输出端子和所述第二电源端子之间的第一N沟道晶体管; 形成在公共体区域上的第一至第五晶体管的公共体P沟道晶体管组; 形成在所述一个节点和所述第二电源端子之间并包括栅电极的第二N沟道晶体管，其提供使能信号的反相信号; 以及逻辑电路，其将所述输入信号的反相信号输入到所述第一P沟道晶体管和所述第一N沟道晶体管的所述栅电极，或者将保持所述第一P沟道晶体管截止的信号输入到栅电极 根据所述使能信号的状态，所述第一P信道。

公开(公告)号：US06211714B1

公开(公告)日：2001-04-03

申请号：US09013679

申请日：1998-01-26

申请人： Deog-Kyoon Jeong

发明人： Deog-Kyoon Jeong

IPC分类号： G06F104

CPC分类号： H04L7/0338 ,  H03K19/018592 ,  H03L7/0891 ,  H03L7/0895 ,  H03L7/0996 ,  H03M9/00 ,  H04J3/047 ,  H04L5/1423 ,  H04L7/0008 ,  H04L7/0337 ,  H04L25/0272 ,  H04L25/0278 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/085

摘要： A system for converting between parallel data and serial data is described. In the system, individual bits of the parallel data are latched into individual registers. Each register is coupled to a corresponding AND gate which is also connected to receive phased clock signals. The output terminals of the AND gates are connected to an OR gate. Using the system, with appropriately phased clocks, the parallel data is converted into serial data.

摘要翻译： 描述用于在并行数据和串行数据之间转换的系统。 在系统中，并行数据的各个位被锁存到各个寄存器中。 每个寄存器耦合到相应的与门，该门也被连接以接收相位时钟信号。 与门的输出端连接到或门。 使用系统，使用适当的相位时钟，并行数据被转换为串行数据。

公开(公告)号：US5877633A

公开(公告)日：1999-03-02

申请号：US839732

申请日：1997-04-15

申请人： Richard Ng ,  Matthew Duane Mottier ,  John Jerome Janssen

发明人： Richard Ng ,  Matthew Duane Mottier ,  John Jerome Janssen

IPC分类号： H03K19/0175 ,  H03K19/0185 ,  H04L5/14 ,  H04L5/16 ,  H04L25/24

CPC分类号： H03K19/018592 ,  H04L25/24 ,  H04L5/1423 ,  H04L5/16

摘要： A bidirectional voltage translator (102) includes a first port (200/400), a second port (202/402) and a bidirectional translator circuit (208-215/404-408, 410, 412-415) coupled between the first and second ports (200/400,202/402). The first and second ports (200/400,202/402) communicate signals at a first voltage level and a second voltage level, respectively. The second voltage level is different from the first voltage level. When a first port signal input at the first voltage level at the first port (200/400) is detected, the bidirectional translator circuit (208-215/404-408, 410, 412-415) translates the first port signal into the second voltage level at the second port (202/402) and disables translation of a signal at the second port (202/402) to the first port (200/400). When a second port signal input at the second voltage level at the second port (202/402) is detected, the bidirectional translator circuit (208-215/404-408, 410, 412-415) translates the second port signal into the first voltage level at the first port (200/400) and disables translation of a signal at the first port (200/400) to the second port (202/402).

摘要翻译： 双向电压转换器（102）包括第一端口（200/400），第二端口（202/402）和双向转换器电路（208-215 / 404-408,410,412-415），其耦合在第一端口 第二个港口（200 / 400,202 / 402）。 第一和第二端口（200 / 400,202 / 402）分别以第一电压电平和第二电压电平传送信号。 第二电压电平与第一电压电平不同。 当检测到在第一端口（200/400）处以第一电压电平输入的第一端口信号时，双向转换器电路（208-215 / 404-408,410,412-415）将第一端口信号转换为第二端口信号 第二端口（202/402）处的电压电平，并禁止在第二端口（202/402）处的信号到第一端口（200/400）的转换。 当检测到在第二端口（202/402）处以第二电压电平输入的第二端口信号时，双向转换器电路（208-215 / 404-408,410,412-415）将第二端口信号转换为第一端口 第一端口（200/400）处的电压电平，并禁用在第一端口（200/400）处的信号到第二端口（202/402）的转换。

公开(公告)号：US5712585A

公开(公告)日：1998-01-27

申请号：US580914

申请日：1995-12-29

申请人： Deog-Kyoon Jeong

发明人： Deog-Kyoon Jeong

IPC分类号： H04L5/22 ,  H03K19/0185 ,  H03L7/089 ,  H03L7/099 ,  H03M9/00 ,  H04J3/04 ,  H04L5/14 ,  H04L7/00 ,  H04L7/033 ,  H04L13/10 ,  H04L25/02 ,  H04L25/08 ,  H04L29/10 ,  H03K1/04

CPC分类号： H04L7/0338 ,  H03K19/018592 ,  H03L7/0996 ,  H03M9/00 ,  H04J3/047 ,  H04L25/0272 ,  H04L25/085 ,  H04L5/1423 ,  H04L7/0337 ,  H03L7/0891 ,  H03L7/0895 ,  H04L25/0278 ,  H04L25/028 ,  H04L25/0292 ,  H04L7/0008

摘要： A system for convening between parallel data and serial data is described. In the system (b 10), individual bits of the parallel data (12) are latched into individual registers (117). Each register (117) is coupled to a corresponding AND gate (110) which is also connected to receive phased clock signals. The output terminals of the AND gates (110) are connected to an OR gate (115). Using the system, with appropriately phased clocks, the parallel data is convened into serial data.

摘要翻译： 描述用于在并行数据和串行数据之间进行转换的系统。 在系统（b 10）中，并行数据（12）的各个比特被锁存到各个寄存器（117）中。 每个寄存器（117）耦合到相应的与门（110），其也连接以接收相位时钟信号。 与门（110）的输出端子连接到或门（115）。 使用系统，使用适当的相位时钟，并行数据被调入串行数据。

公开(公告)号：US5583454A

公开(公告)日：1996-12-10

申请号：US566131

申请日：1995-12-01

申请人： Keith G. Hawkins ,  Harikumar B. Nair ,  Shivachandra I. Javalagi ,  Kuok Y. Ling

发明人： Keith G. Hawkins ,  Harikumar B. Nair ,  Shivachandra I. Javalagi ,  Kuok Y. Ling

IPC分类号： H03K3/356 ,  H03K19/003 ,  H03K19/0185 ,  H03K19/0175

CPC分类号： H03K19/018585 ,  H03K19/00315 ,  H03K19/018592 ,  H03K3/356182

摘要： An integrated circuit is presented having a driver circuit programmable to produce a variety of output voltages and conductive to the voltage levels of circuits interfaced by the integrated circuit. The integrated circuit includes programmable pullup and pulldown functions. The integrated circuit may be configured into an application having devices powered by a power supply voltage which is substantially larger than the voltage supplying the core section of the integrated circuit. Additionally, the present integrated circuit may be configured into other applications having devices powered by a power supply voltage substantially similar to the voltage supplying the integrated circuit core section. The present integrated circuit therefore retains utility for a large variety of applications. The pullup and pulldown transistors may be programmed to provide a resistive one, resistive zero, or neither.

摘要翻译： 提出了一种集成电路，其具有可编程的驱动器电路，以产生各种输出电压并且与由集成电路接口的电路的电压电平导通。 集成电路包括可编程上拉和下拉功能。 集成电路可以被配置为具有由比该集成电路的芯部提供的电压大得多的电源电压供电的装置的应用。 此外，本集成电路可以被配置成具有由基本上类似于提供集成电路核心部分的电压的电源电压供电的装置的其他应用。 因此，本集成电路可以用于各种各样的应用。 上拉和下拉晶体管可以被编程为提供电阻一个，电阻零或两者。

公开(公告)号：US5300835A

公开(公告)日：1994-04-05

申请号：US16574

申请日：1993-02-10

申请人： Mahmud Assar ,  Prakash C. Agarwal ,  Vlad Bril

发明人： Mahmud Assar ,  Prakash C. Agarwal ,  Vlad Bril

IPC分类号： H01L27/118 ,  H03K19/00 ,  H03K19/0185 ,  H03K19/0175

CPC分类号： H03K19/018521 ,  H01L27/11898 ,  H03K19/0027 ,  H03K19/018585 ,  H03K19/018592 ,  H03K2217/0018

摘要： This invention describes the design and implementation of a low power CMOS bidirectional I/O buffer that translates low voltage core logic level signals into the highest logic level signals to drive the final output stage which outputs a selectable logic level signal. The invention further translates input signals of a variety of logic levels into low voltage core logic level signals. In either case, AC and DC power consumption is minimized in a mixed power supply environment that requires voltage translation to represent the proper binary logic levels.

摘要翻译： 本发明描述了低功率CMOS双向I / O缓冲器的设计和实现，其将低电压核心逻辑电平信号转换为最高逻辑电平信号以驱动输出可选逻辑电平信号的最终输出级。 本发明还将各种逻辑电平的输入信号转换为低电压核心逻辑电平信号。 在任一情况下，在需要电压转换来表示适当的二进制逻辑电平的混合电源环境中AC和DC功耗被最小化。

公开(公告)号：US5243623A

公开(公告)日：1993-09-07

申请号：US588011

申请日：1990-09-25

申请人： Gary S. Murdock

发明人： Gary S. Murdock

IPC分类号： H04L5/14 ,  G06F13/16 ,  G06F13/40 ,  H03K19/0175 ,  H03K19/0185 ,  H04L25/02

CPC分类号： H03K19/018592 ,  G06F13/4072 ,  H03K19/018585

摘要： A transceiver interface device in accordance with the present invention includes features which allow the transceiver to be switched for operation in either a differential or a single-ended mode. First, the output levels of the transceiver's differential line driver are switchable between TTL levels and non-TTL levels with small differential swings. Second, the transceiver's differential receiver is switchable between a differential threshold and a single-ended TTL threshold. Third, while in differential mode, both outputs of the driver may be placed in the high impedance state or active at the same time, but it is also possible to switch to a single-ended mode in which one driver output is in the high impedance state while the other can be switched between being active or being in the high impedance state. Fourth, the transceiver uses the SCSI standard DIFFSENS pin or driver enable signal for switching between differential mode and single-ended mode operation.

公开(公告)号：US5084637A

公开(公告)日：1992-01-28

申请号：US358321

申请日：1989-05-30

申请人： Roger P. Gregor

发明人： Roger P. Gregor

IPC分类号： H03K19/0185

CPC分类号： H03K19/018592

摘要： A bidirectional level shifting interface circuit has first and second I/O ports and an FET with a drain-source channel connected between the first and second I/O ports. The first I/O port is connected to an I/O port of a first digital circuit operating at a relatively low supply voltage, and the second I/O port is connected to an I/O port of a second digital circuit operating at a relatively high supply voltage. This channel passes communication signals in each direction between the first and second digital circuit. A latching circuit comprising a P Channel FET is biased by the relatively high voltage supply, has an output connected to the second I/O port, and has a control input. The interface circuit further comprises an inverter circuit having a control input connected to the second I/O port and an inverted output connected to the control input of the latching FET such that when the second I/O port exhibits a binary one voltage caused by the first digital circuit, the inverted output exhibits a binary zero voltage to activate the P Channel FET to latch the second I/O port at sufficient voltage to drive the second digital circuit at binary one level.

摘要翻译： 双向电平移位接口电路具有第一和第二I / O端口以及连接在第一和第二I / O端口之间的漏极 - 源极通道的FET。 第一I / O端口连接到在较低电源电压下工作的第一数字电路的I / O端口，而第二I / O端口连接到第二数字电路的I / O端口 电源电压相对较高。 该通道在第一和第二数字电路之间的每个方向上通过通信信号。 包括P沟道FET的锁存电路被相对高的电压源偏置，具有连接到第二I / O端口的输出，并具有控制输入。 接口电路还包括具有连接到第二I / O端口的控制输入和连接到锁存FET的控制输入的反相输出的反相器电路，使得当第二I / O端口呈现由 第一数字电路，反相输出显示二进制零电压以激活P沟道FET以在足够的电压下锁存第二I / O端口，以二进制一级驱动第二数字电路。

公开(公告)号：US5019728A

公开(公告)日：1991-05-28

申请号：US580017

申请日：1990-09-10

申请人： Ikuo J. Sanwo ,  James A. Donahue

发明人： Ikuo J. Sanwo ,  James A. Donahue

IPC分类号： G06F3/00 ,  H03K19/0185

CPC分类号： H03K19/018528 ,  H03K19/018592

摘要： In a high speed complementary metal-oxide-semiconductor (CMOS) inter-integrated circuit (IC) chip communication system, transmission line voltage swings between logic high and logic low levels are reduced by defining minimum and maximum bus voltages which lie between CMOS logic levels, thus lowering bus transition and hence data transfer times. The system is versatile, and does not involve typical emitter-coupled logic (ECL) logic levels. Transceivers interfacing between IC chips and the backpanel transmit data in the reduced logic level range on a pre-charged transmission line, and receive and convert data back to CMOS levels. A limiting transistor in the transmitter portion of the transceiver limits logic low level of the transmission line. The receiver portion of the transceiver converts the voltages received to CMOS levels with the aid of a differential (sense) amplifier.

摘要翻译： 在高速互补金属氧化物半导体（CMOS）集成电路（IC）芯片通信系统中，通过定义位于CMOS逻辑电平之间的最小和最大总线电压来降低逻辑高电平和逻辑低电平之间的传输线电压摆幅 ，从而降低总线转换，从而降低数据传输时间。 该系统是通用的，不涉及典型的发射极耦合逻辑（ECL）逻辑电平。 IC芯片和背板之间的接收器在预充电传输线路上以降低的逻辑电平范围传输数据，并将数据接收并转换回CMOS电平。 收发器的发射器部分中的限制晶体管限制传输线的逻辑低电平。 收发器的接收器部分借助于差分（感测）放大器将接收的电压转换为CMOS电平。

公开(公告)号：US11973499B1

公开(公告)日：2024-04-30

申请号：US18059764

申请日：2022-11-29

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Deric Wayne Waters ,  Roland Son ,  Sualp Aras ,  Ralph Braxton Wade, III

IPC分类号： H03K19/0185 ,  G01R19/10

CPC分类号： H03K19/018592 ,  G01R19/10 ,  H03K19/018507

摘要： A bidirectional level shifter circuit includes first and second driver circuits, first and second comparators, and a control circuit. The first driver circuit includes a first driver output and a first enable input. The second driver circuit includes a second driver output and a second enable input. The first comparator includes a first comparator output, a first reference input, and a first comparator input that is coupled to the second driver output. The second comparator includes a second comparator output, a second reference input, and a second comparator input is coupled to the first driver output. The control circuit includes a first control input coupled to the first comparator output, a second control input coupled to the second comparator output, a first control output coupled to the first enable input, and a second control output coupled to the second enable input.