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    SYSTEMS AND METHODS FACILITATING REDUCED LATENCY VIA STASHING IN SYSTEM ON CHIPS
    111.
    发明申请
    SYSTEMS AND METHODS FACILITATING REDUCED LATENCY VIA STASHING IN SYSTEM ON CHIPS 有权
    系统和方法通过在系统中的堆栈来实现减少的延迟

    公开(公告)号：US20170010966A1

    公开(公告)日：2017-01-12

    申请号：US14796167

    申请日：2015-07-10

    Applicant: APPLIED MICRO CIRCUITS CORPORATION

    Inventor： Millind Mittal

    IPC: G06F12/08

    CPC classification number: G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0875 ,  G06F2212/1024 ,  G06F2212/251 ,  G06F2212/452 ,  G06F2212/602

    Abstract: Systems and methods that facilitate reduced latency via stashing in multi-level cache memory architectures of systems on chips (SoCs) are provided. One method involves stashing, by a device includes a plurality of multi-processor central processing unit cores, first data into a first cache memory of a plurality of cache memories, the plurality of cache memories being associated with a multi-level cache memory architecture. The method also includes generating control information including: a first instruction to cause monitoring contents of a second cache memory of the plurality of cache memories to determine whether a defined condition is satisfied for the second cache memory; and a second instruction to cause prefetching the first data into the second cache memory of the plurality of cache memories based on a determination that the defined condition is satisfied.

    Abstract translation: 提供了通过堆叠在片上系统（SoC）的多级高速缓存存储器体系结构中促进减少延迟的系统和方法。 一种方法涉及通过设备包括多个多处理器中央处理单元核心的第一数据进入多个高速缓存存储器中的第一高速缓存存储器，所述多个高速缓冲存储器与多级高速缓冲存储器结构相关联。 该方法还包括产生控制信息，该控制信息包括：第一指令，用于使多个高速缓存存储器中的第二高速缓存存储器的内容的监视，以确定对于第二高速缓冲存储器是否满足定义的条件; 以及第二指令，用于基于满足所定义的条件的确定，将所述第一数据预取到所述多个高速缓冲存储器的第二高速缓冲存储器中。

    Product coded modulation scheme based on leech lattice and binary and nonbinary codes
    112.
    发明授权
    Product coded modulation scheme based on leech lattice and binary and nonbinary codes 有权
    基于水蛭晶格和二进制和非二进制代码的商品编码调制方案

    公开(公告)号：US09467177B1

    公开(公告)日：2016-10-11

    申请号：US14466355

    申请日：2014-08-22

    Applicant: APPLIED MICRO CIRCUITS CORPORATION

    Inventor： Dariush Dabiri

    IPC: H03M13/00 ,  H03M13/29

    CPC classification number: H03M13/2906 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/251 ,  H03M13/3746 ,  H03M13/616 ,  H03M13/6325 ,  H04L1/00 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0057

    Abstract: A transceiver architecture contains an encoder and a decoder for communicating high speed transmissions. The encoder modulates signal data based on an FEC code that has a symbol size that is not matched to a symbol size of a hexacode. Any code where the symbol size is less than the sample size for coding can be serially concatenated. During decoding the multilevel decoding leech lattice and FEC decoder iteratively passes their outputs back and forth to each other until the encoded bits are decoded.

    Abstract translation: 收发机架构包含用于传送高速传输的编码器和解码器。 编码器基于具有与六进制码的符号大小不匹配的符号大小的FEC码来对信号数据进行调制。 符号大小小于编码的样本大小的任何代码都可以串行连接。 在解码期间，多级解码水蛭格和FEC解码器将它们的输出相互反复地传递给彼此直到编码比特被解码。

    High efficiency half-cross-coupled decoupling capacitor
    113.
    发明授权
    High efficiency half-cross-coupled decoupling capacitor 有权
    高效半交叉耦合去耦电容

    公开(公告)号：US09438225B1

    公开(公告)日：2016-09-06

    申请号：US14736882

    申请日：2015-06-11

    Applicant: APPLIED MICRO CIRCUITS CORPORATION

    Inventor： Alfred Yeung ,  Ronen Cohan

    IPC: H03K17/16

    CPC classification number: H01L27/0248

    Abstract: A decoupling capacitor circuit design facilitates high operational frequency without sacrificing area efficiency. In order to disassociate the sometimes opposing design criteria of high operational frequency and area efficiency, a p-channel field effect transistor (PFET) and an n-channel field effect transistor are connected in a half-cross-coupled (HCC) fashion. The HCC circuit is then supplemented by at least one area efficient capacitance (AEC) device. The half-cross-coupled transistors address the high frequency design requirement, while the AEC device(s) address the high area efficiency requirement. The design eliminates the undesirable trade-off between operating frequency and area efficiency inherent in some conventional DCAP designs.

    Abstract translation: 去耦电容电路设计有助于高工作频率，而不牺牲面积效率。 为了解决高操作频率和面积效率的有时相反的设计标准，p沟道场效应晶体管（PFET）和n沟道场效应晶体管以半交叉耦合（HCC）方式连接。 然后，HCC电路由至少一个区域有效电容（AEC）装置补充。 半交叉耦合晶体管满足高频设计要求，而AEC器件满足高区域效率要求。 该设计消除了一些常规DCAP设计中固有的工作频率和面积效率之间的不利权衡。

    Method and apparatus for gapping
    114.
    发明授权
    Method and apparatus for gapping 有权
    缝合方法和装置

    公开(公告)号：US09369135B2

    公开(公告)日：2016-06-14

    申请号：US13846171

    申请日：2013-03-18

    Applicant: Applied Micro Circuits Corporation

    Inventor： Yehuda Azenkot ,  Michael Grosner ,  Timothy P. Walker

    IPC: H03B19/00 ,  H03L7/06

    CPC classification number: H03L7/06

    Abstract: Systems and methods for generating gapped signals comprising a Delta Sigma Modulator (DSM) configured to generate gapping control signals used to control gap removal rates of an associated gapping unit. The DSM is configured to generate a gapping control signal based on a value of an overflow resulted from performing adding a first number with a remainder of a stored value modulo a second number. The gap removal rates as well as the gap removal resolutions can be adjusted by selecting appropriate values of the first number, the stored value, and the second number. The gapping resolution can be a portion of a pulse. The first number and the second number may be derived from an intended frequency ratio between a gapped signal and a corresponding input signal. The gapping unit may comprise a gapping circuit or a multi-modulus divider.

    Abstract translation: 用于产生有间隙信号的系统和方法包括配置成产生用于控制相关间隙单元的间隙去除速率的间隙控制信号的ΔΣ调制器（DSM）。 DSM被配置为基于通过执行将具有第二数量的存储值的剩余部分的第一数字相加的溢出的值来生成间隙控制信号。 可以通过选择第一个数字，存储值和第二个数字的适当值来调整间隙去除率以及间隙去除分辨率。 间隙分辨率可以是脉冲的一部分。 第一数字和第二数字可以从有间隙信号和对应的输入信号之间的预期频率比率导出。 间隙单元可以包括间隙电路或多模式分配器。

    Reformating a plurality of signals to generate a combined signal comprising a higher data rate than a data rate associated with the plurality of signals
    115.
    发明授权
    Reformating a plurality of signals to generate a combined signal comprising a higher data rate than a data rate associated with the plurality of signals 有权
    重新形成多个信号以产生包括比与多个信号相关联的数据速率更高的数据速率的组合信号

    公开(公告)号：US09246617B2

    公开(公告)日：2016-01-26

    申请号：US14021035

    申请日：2013-09-09

    Applicant: APPLIED MICRO CIRCUITS CORPORATION

    Inventor： Francesco Caggioni ,  Dimitrios Giannakopoulos

    IPC: H04J3/02 ,  H04J3/16

    CPC classification number: H04J3/16 ,  H04J3/07

    Abstract: Various aspects provide for aggregating a plurality of signals to generate a combined signal. An aggregation component is configured for reformatting a plurality of first signals and combining the plurality of first signals to generate a combined signal that comprises a higher data rate than a data rate associated with the plurality of first signals. A transmitter component is configured for receiving the combined signal and generating one or more data streams based on the combined signal. In an aspect, the aggregation component is additionally configured for reformatting and/or combining the plurality of first signals and at least one second signal to generate the combined signal. In another aspect, a receiver component is configured for generating a pseudo signal at a data rate of the combined signal. In yet another aspect, a de-aggregation component is configured for recovering the plurality of first signals and/or the at least one second signal from the pseudo signal.

    Abstract translation: 各种方面提供聚合多个信号以产生组合信号。 配置聚合组件用于重新格式化多个第一信号并组合多个第一信号以产生包括比与多个第一信号相关联的数据速率更高的数据速率的组合信号。 发射机组件被配置用于接收组合信号并且基于组合信号产生一个或多个数据流。 在一方面，聚合组件另外被配置用于重新格式化和/或组合多个第一信号和至少一个第二信号以产生组合信号。 在另一方面，接收机组件被配置为以组合信号的数据速率产生伪信号。 在另一方面，解聚合组件被配置用于从伪信号中恢复多个第一信号和/或至少一个第二信号。

    PULSE-LATCH BASED BUS DESIGN FOR INCREASED BANDWIDTH
    116.
    发明申请
    PULSE-LATCH BASED BUS DESIGN FOR INCREASED BANDWIDTH 审中-公开
    基于PULSE-LATCH的总线设计，增加带宽

    公开(公告)号：US20150363352A1

    公开(公告)日：2015-12-17

    申请号：US14482780

    申请日：2014-09-10

    Applicant: Applied Micro Circuits Corporation

    Inventor： Arun JANGITY

    IPC: G06F13/42 ,  G06F13/16

    CPC classification number: G06F13/16 ,  G11C5/063 ,  G11C7/1039 ,  G11C7/1048 ,  G11C7/222

    Abstract: A memory bus comprising a plurality of latches arranged sequentially between a source node and a destination node of a channel of the memory bus; and a pulse generator. The pulse generator is operable to generate a sequence of pulses, each sequential pulse to be simultaneously received by the plurality of latches. A pulse is generated for each edge of a clock signal. A first latch of the plurality of latches is operable to pass on a first data sample while a first pulse is received by the first latch of the plurality of latches. A second latch of the plurality of latches is operable to pass on a second data sample towards the first latch of the plurality of latches while the first pulse is simultaneously received by the first and second latches of the plurality of latches.

    Abstract translation: 存储器总线，包括顺序地布置在存储器总线的通道的源节点和目的地节点之间的多个锁存器; 和脉冲发生器。 脉冲发生器可操作以产生脉冲序列，每个顺序脉冲将由多个锁存器同时接收。 为时钟信号的每个边沿产生一个脉冲。 当多个锁存器的第一锁存器接收到第一脉冲时，多个锁存器的第一锁存器可操作以传递第一数据采样。 多个锁存器的第二锁存器可操作以使第二数据采样朝着多个锁存器的第一锁存器传递，同时第一脉冲由多个锁存器的第一和第二锁存器同时接收。

    SYSTEMS AND METHODS FACILITATING MULTI-WORD ATOMIC OPERATION SUPPORT FOR SYSTEM ON CHIP ENVIRONMENTS
    119.
    发明申请
    SYSTEMS AND METHODS FACILITATING MULTI-WORD ATOMIC OPERATION SUPPORT FOR SYSTEM ON CHIP ENVIRONMENTS 审中-公开
    系统和方法，促进芯片环境系统的多重原理操作支持

    公开(公告)号：US20150324133A1

    公开(公告)日：2015-11-12

    申请号：US14264716

    申请日：2014-04-29

    Applicant: APPLIED MICRO CIRCUITS CORPORATION

    Inventor： Millind Mittal

    IPC: G06F3/06

    CPC classification number: G06F9/3834 ,  G06F3/0613 ,  G06F3/0655 ,  G06F3/0671

    Abstract: Systems and methods that facilitate multi-word atomic operation support for systems on chip are described. One method involves: receiving an instruction associated with a calling process, and determining a first memory width associated with execution of the instruction based on an operator of the instruction and a width of at least one operand of the instruction. The instruction can be associated with an atomic operation. In some embodiments, the instruction contains a message having a first field identifying the operator and a second field identifying the operand.

    Abstract translation: 描述了促进片上系统的多字母原子操作支持的系统和方法。 一种方法包括：接收与呼叫过程相关联的指令，以及基于所述指令的操作符和所述指令的至少一个操作数的宽度来确定与所述指令的执行相关联的第一存储器宽度。 该指令可以与原子操作相关联。 在一些实施例中，指令包含具有标识操作者的第一字段和标识操作数的第二字段的消息。

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