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    SILICON WAFER THINNING END POINT METHOD
    111.
    发明申请
    SILICON WAFER THINNING END POINT METHOD 有权
    硅氧化薄点法

    公开(公告)号：US20080124896A1

    公开(公告)日：2008-05-29

    申请号：US11563715

    申请日：2006-11-28

    Applicant: Steven R. Codding ,  Timothy C. Krywanczyk ,  Edmund J. Sprogis

    Inventor： Steven R. Codding ,  Timothy C. Krywanczyk ,  Edmund J. Sprogis

    IPC: H01L21/461

    CPC classification number: H01L21/78

    Abstract: Disclosed are a method of and system for fabricating a semiconductor wafer. The method comprises the steps of providing a silicon wafer having a front side an a back side, building an integrated circuit on the front side of the wafer, and thereafter removing substrate from the back side of the silicon wafer. The building step includes the steps of forming a desired structure in the wafer, and forming an end structure in the wafer, said end structure extending to a greater depth, toward the back side of the wafer, than the desired structure. Also, the removing step includes the step of removing said substrate only to the end structure, whereby no part of the desired structure is removed during the removing step.

    Abstract translation: 公开了用于制造半导体晶片的方法和系统。 该方法包括以下步骤：提供具有正面和背面的硅晶片，在晶片前侧构建集成电路，然后从硅晶片的背面去除衬底。 构建步骤包括以下步骤：在晶片中形成期望的结构，并且在晶片中形成端部结构，所述端部结构延伸到比晶片的背面更大的深度，而不是期望的结构。 此外，除去步骤包括仅将该基材除去至端部结构的步骤，由此在除去步骤期间不除去所需结构的一部分。

    Method for thinning wafers that have contact bumps
    113.
    发明授权
    Method for thinning wafers that have contact bumps 失效
    稀释具有接触凸点的晶片的方法

    公开(公告)号：US07135124B2

    公开(公告)日：2006-11-14

    申请号：US10713659

    申请日：2003-11-13

    Applicant: Timothy C. Krywanczyk ,  Edmund J. Sprogis

    Inventor： Timothy C. Krywanczyk ,  Edmund J. Sprogis

    IPC: H01L21/302 ,  C23F1/00 ,  B24B1/00

    CPC classification number: H01L21/78

    Abstract: In accordance with the foregoing objects and advantages, the present invention provides a fabrication device that may be used during the grinding operation of the fabrication process. The fabrication device comprises a socket plate that includes a plurality of cavities formed therein that correspond in position and number to the solder (or other conductive material) bumps formed on the front surface of a product wafer.

    Abstract translation: 根据上述目的和优点，本发明提供了可在制造过程的磨削操作期间使用的制造装置。 该制造装置包括插座板，该插座板包括形成在其中的多个空腔，其位置和数量与形成在产品晶片的前表面上的焊料（或其他导电材料）凸起相对应。

    Hybrid open folded sense amplifier architecture for a memory device
    118.
    发明授权
    Hybrid open folded sense amplifier architecture for a memory device 失效
    用于存储器件的混合开放式折叠式放大器架构

    公开(公告)号：US5276641A

    公开(公告)日：1994-01-04

    申请号：US806027

    申请日：1991-12-12

    Applicant: Edmund J. Sprogis ,  Hing Wong

    Inventor： Edmund J. Sprogis ,  Hing Wong

    IPC: G11C11/401 ,  G11C11/4096 ,  G11C11/4097 ,  G11C13/00

    CPC classification number: G11C11/4097 ,  G11C11/4096

    Abstract: A hybrid open/folded bit line sense amplifier arrangement and accompanying circuitry primarily for use on a ULSI DRAM memory chip to reduce the area needed for a memory cell and eliminate noise between bit lines. The circuitry includes two memory arrays containing a plurality of memory cells interconnected by a plurality of bit lines and word lines. In the preferred embodiment, the memory cells are accessible on every two out of three bit lines encountered by a word line. A set of open bit line sense amplifiers each with two connectors, one multiplexed to a number of bit lines in the first array and the other multiplexed to a number of bit lines in the second array is provided. Each memory array has a set of folded bit line sense amplifiers with two connectors each connector multiplexed to a number of bit lines in the array. The control circuitry with multiplexing ensures that the connectors of the sense amplifiers access only one bit lines at a time. The accessed by the connectors of each folded line sense amplifier are non-adjacent and simultaneously therewith, a connector of an open bit sense amplifier accesses a bit line between the bit lines accessed by the folded sense amplifier. In the preferred embodiment each connector of a sense amplifier is multiplexed to three bit lines. In a second version the connectors are multiplexed to two bit lines.

    Abstract translation: 混合的开/折位线读出放大器装置和主要用于ULSI DRAM存储器芯片的相关电路，以减少存储器单元所需的面积并消除位线之间的噪声。 电路包括两个存储器阵列，其包含由多个位线和字线互连的多个存储器单元。 在优选实施例中，存储器单元可以通过字线遇到的三个位线中的每两个进行访问。 提供了一组开放位线读出放大器，每个具有两个连接器，一个复用到第一阵列中的多个位线，另一个复用到第二阵列中的多个位线。 每个存储器阵列具有一组具有两个连接器的折叠位线读出放大器，每个连接器被多路复用到阵列中的多个位线。 具有复用的控制电路确保了读出放大器的连接器一次仅访问一个位线。 由每个折叠线检测放大器的连接器访问的是不相邻的，并且同时，开放位读出放大器的连接器访问由折叠读出放大器访问的位线之间的位线。 在优选实施例中，读出放大器的每个连接器被复用到三个位线。 在第二个版本中，连接器被复用到两个位线。

    Semiconductor defect monitor for diagnosing processing-induced defects
    119.
    发明授权
    Semiconductor defect monitor for diagnosing processing-induced defects 失效
    用于诊断加工引起的缺陷的半导体缺陷监测器

    公开(公告)号：US4801869A

    公开(公告)日：1989-01-31

    申请号：US42906

    申请日：1987-04-27

    Applicant: Edmund J. Sprogis

    Inventor： Edmund J. Sprogis

    IPC: H01L21/66 ,  G01R31/02 ,  G01R31/28 ,  G11C29/24 ,  G01R31/00 ,  G11C7/00

    CPC classification number: G01R31/2831 ,  G01R31/024 ,  G01R31/2884 ,  G11C29/24

    Abstract: A semiconductor-processing defect monitor construction for diagnosing processing-induced defects. The semiconductor-processing defect monitor utilizes an array layout and includes continuity defect monitoring structures and short-circuit defect monitoring structures. Once a defect has been indicated by a testing operation, the array layout associated with the defect monitor can be used quickly to determine the approximate location of the known defect, thereby facilitating prompt visual observation of the known defect and, thus, prompt determination of the appropriate corrective action to be applied before substantial continued manufacturing has occurred.

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