公开(公告)号：US10855946B2

公开(公告)日：2020-12-01

申请号：US15374534

申请日：2016-12-09

Applicant: Socionext Inc.

Inventor： Yoshinori Okajima ,  Masaki Toyokura ,  Masayuki Taniyama ,  Masahiro Takeuchi ,  Takashi Akiyama

IPC: H04N5/445 ,  G09G5/14 ,  H04N13/398 ,  H04N21/442 ,  H04N21/4402 ,  H04N13/296 ,  H04N13/279 ,  H04N21/4223 ,  H04N13/368 ,  H04N13/383

Abstract: Disclosed herein is a semiconductor integrated circuit which controls the quality of an image and includes a viewer detector, a region specifier, and a controller. The viewer detector detects the number of viewer(s) watching the image and a gaze region being watched by the viewer within the image. If the number of viewers is plural, the region specifier specifies a local region of the image as a target region based on a plurality of gaze regions being watched by the viewers. The controller performs image quality control on the target region.

公开(公告)号：US10825760B2

公开(公告)日：2020-11-03

申请号：US16165486

申请日：2018-10-19

Applicant: SOCIONEXT INC.

Inventor： Toshihiro Nakamura ,  Isao Motegi ,  Noriyuki Shimazu ,  Masanobu Hirose ,  Taro Fukunaga

IPC: H01L23/498 ,  H01L23/00

Abstract: A semiconductor chip having a core region and an I/O region which surrounds the core region is provided with a plurality of external connection pads connected to I/O cells. The plurality of external connection pads include a first pad group comprised of the external connection pads connected to the same node, and a second pad group comprised of the external connection pads connected to respective different nodes. In first and second pad groups, the external connection pads are arranged in an X direction along an external side of the semiconductor chip, and a pad arrangement pitch in the first pad group is smaller than that in the second pad group.

公开(公告)号：US20200304612A1

公开(公告)日：2020-09-24

申请号：US16896490

申请日：2020-06-09

Applicant: SOCIONEXT INC.

Inventor： Teruaki HASEGAWA ,  Kouichi TSUTSUMI

IPC: H04L29/08 ,  H04N21/434 ,  H04N21/43 ,  H04L1/00 ,  H04J3/06

Abstract: A method of transmitting a data signal in sync with a clock signal in a DTV receiver. The method includes performing demodulation processing and error correction processing on an input carrier wave and outputting signals resulting from these types of processing; acquiring a transport stream (TS) packet included in the signals; acquiring a variable-length packet included in the signals; and selecting either the TS packet or the variable-length packet and outputting the selected packet as the data signal, where to variable-length packet is either a type length value (TLV) packet or an Internet protocol (IP) packet.

公开(公告)号：US20200302069A1

公开(公告)日：2020-09-24

申请号：US16899256

申请日：2020-06-11

Applicant: SOCIONEXT INC.

Inventor： Seiji Goto ,  Eiichi NIMODA

IPC: G06F21/60 ,  G06F9/4401 ,  G06F11/07

Abstract: In a processing apparatus having semiconductor integrated circuits, a first status monitoring circuit included in a first semiconductor integrated circuit is configured to instruct a plurality of second semiconductor integrated circuits to transmit status information indicating statuses of the plurality of second semiconductor integrated circuits. When a second status monitoring circuit included in each of the plurality of second semiconductor integrated circuits receives the instruction for transmission of the corresponding status information, the second status monitoring circuit transmits encrypted information in which the status information is encrypted to the first semiconductor integrated circuit.

公开(公告)号：US10784887B2

公开(公告)日：2020-09-22

申请号：US16719741

申请日：2019-12-18

Applicant: SOCIONEXT INC.

Inventor： Suhas Rattan

IPC: H03M1/78 ,  H03M1/38 ,  H03M1/06 ,  H03M1/80 ,  H03M1/12 ,  H03M1/00

Abstract: Controllable voltage-signal generation circuitry, including: a plurality of segment nodes connected together in series, each adjacent pair of segment nodes connected together via a corresponding coupling capacitor, an end one of the segment nodes serving as an output node; for each of the segment nodes, at least one segment capacitor having a first terminal connected to that segment node and a second terminal connected to a corresponding switch; and switch control circuitry, wherein: each switch is operable to connect the second terminal to one reference voltage source and then instead to another reference voltage source, to apply a voltage change at the second terminal; the reference voltage sources and switches configured such that for each segment node the same voltage change in magnitude is applied by each switch, and such that the voltage change is different in magnitude from the voltage change applied by each switch of another segment node.

公开(公告)号：US20200296371A1

公开(公告)日：2020-09-17

申请号：US16890292

申请日：2020-06-02

Applicant: Socionext Inc.

Inventor： Yoichi AZUKIZAWA

IPC: H04N19/122 ,  H04N19/167 ,  H04N19/176 ,  H04N19/625

Abstract: An encoding method for encoding an image using an inter-picture prediction includes determining a prediction block on which the inter-picture prediction is to be performed, partitioning the prediction block into a plurality of transform blocks by a partitioning method that partitions the prediction block, so that boundaries of the plurality of transform blocks are symmetrical with respect to a horizontal line passing a center of the prediction block and are symmetrical with respect to a vertical line passing the center of the prediction block, the plurality of transform blocks being rectangular, and determining, for each of the plurality of transform blocks, an orthogonal transformation type used for each of a vertical direction and a horizontal direction of a given transform block of the plurality of transform blocks based on a positional relation between the given transform block and the center of the prediction block.

公开(公告)号：US20200243128A1

公开(公告)日：2020-07-30

申请号：US16847551

申请日：2020-04-13

Applicant: Socionext Inc.

Inventor： Masataka Sato ,  Hideo Akiyoshi ,  Masanobu Hirose ,  Yoshinobu Yamagami

IPC: G11C11/408 ,  G11C11/4099 ,  G11C5/02

Abstract: First and second memory cell arrays each having memory cells arranged in the X and Y directions lie side by side in the Y direction with space between them. A relay buffer is provided between first and second row decoders for buffering a control signal to be supplied to the second row decoder. An inter-array block between the first and second memory cell arrays is constituted by at least either a tap cell or a dummy memory cell. The relay buffer and the inter-array block are the same in position and size in the Y direction.

公开(公告)号：US10700095B2

公开(公告)日：2020-06-30

申请号：US16228319

申请日：2018-12-20

Applicant: SOCIONEXT INC.

Inventor： Toshio Hino ,  Junji Iwahori

IPC: H01L27/118 ,  H01L29/423 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/775 ,  H01L29/08 ,  B82Y10/00 ,  H01L29/06 ,  H01L27/092 ,  H01L29/786 ,  H01L27/02

Abstract: A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.

公开(公告)号：US10692856B2

公开(公告)日：2020-06-23

申请号：US16441361

申请日：2019-06-14

Applicant: SOCIONEXT INC.

Inventor： Koichi Taniguchi ,  Masato Maede

IPC: H01L27/02 ,  H01L29/06 ,  H03K3/354 ,  H01L27/092 ,  H01L23/544 ,  H01L23/50 ,  H01L23/528

Abstract: A semiconductor chip including an internal circuit, a plurality of electrode pads and a plurality of I/O cells. The plurality of electrode pads are arranged on a first line, a second line and a third line. Each of the plurality of electrode pads arranged at least on the first and second lines overlaps corresponding one of the plurality of I/O cells in a plan view. The plurality of I/O cells are provided on a peripheral region of the semiconductor chip. Each of the plurality of I/O cells includes a protective circuit, and is connected to corresponding one of the plurality of electrode pads. The protective circuit includes a power source-side protective circuit provided between the corresponding one of the plurality of electrode pads and a power source wiring; and a ground-side protective circuit provided between the corresponding one of the plurality of electrode pads and a ground wiring.

公开(公告)号：US10672720B2

公开(公告)日：2020-06-02

申请号：US16158611

申请日：2018-10-12

Applicant: SOCIONEXT INC.

Inventor： Tomoyuki Yamada ,  Fumio Ushida ,  Shigetoshi Takeda ,  Tomoharu Awaya ,  Koji Banno ,  Takayoshi Minami

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/58 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer.