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公开(公告)号：US11114518B2
公开(公告)日：2021-09-07
申请号：US15779658
申请日：2017-11-07
Inventor： Benlian Wang , Li Wang , Yipeng Chen , Yueping Zuo , Zheng Liu
Abstract: The application discloses a wiring structure, a display substrate and a display device. The wiring structure provided includes a plurality of hollowed pattern strings, each hollowed pattern string including a plurality of hollowed patterns arranged sequentially in a length extension direction of the wiring structure, each hollowed pattern including a hollowed region and a non-hollowed region. The non-hollowed region of any hollowed pattern in a hollowed pattern string at least partially overlaps the non-hollowed region of a hollowed pattern in a further hollowed pattern string adjacent to the hollowed pattern string, and the hollowed regions of the hollowed patterns in the plurality of hollowed pattern strings do not overlap each other. The wiring structure is particularly adapted for flexible display.
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公开(公告)号：US20210012687A1
公开(公告)日：2021-01-14
申请号：US16916910
申请日：2020-06-30
Applicant: BOE Technology Group Co. Ltd.
Inventor： Xiaolong LI , Meng Zhao , Zheng Liu , Chunyang Wang , Mingxin Zhang
Abstract: The present disclosure discloses a display panel and a detecting method thereof. By providing at least one resistance sensor in a bending region, an extending direction of the resistance sensor is perpendicular to an extending direction of an axis for bending and overlaps with the axis for bending. By electrically connecting the resistance sensor to a detecting circuit, a change of the resistance value of the resistance sensor can be reflected as a change of voltage.
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公开(公告)号：US10466552B2
公开(公告)日：2019-11-05
申请号：US15564661
申请日：2017-05-19
Inventor： Shoukun Wang , Huibin Guo , Yuchun Feng , Liangliang Li , Zheng Liu
IPC: H01L27/14 , H01L29/04 , H01L29/15 , H01L31/036 , G02F1/1362 , G02F1/1368 , H01L27/12 , H01L29/786 , G02F1/1343
Abstract: An array substrate, a display device, and a method for manufacturing the array substrate are disclosed. The array substrate includes a base substrate and a pixel array structure disposed on the base substrate, the pixel array structure includes at least one light shielding layer made of a light shielding material, and the light shielding material can prevent light leakage or light reflection, thereby increasing an opening ratio of the display device.
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114.发明授权公开(公告)号：US10431669B2
公开(公告)日：2019-10-01
申请号：US15116980
申请日：2015-10-16
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Xiaolong Li , Zheng Liu , Xiaoyong Lu , Dong Li , Chunping Long
IPC: H01L29/66 , H01L21/20 , H01L21/265 , H01L21/28 , H01L27/12 , H01L29/06 , H01L29/786
Abstract: A manufacturing method for a polysilicon thin film is provided. The manufacturing method for a polysilicon thin film includes forming a polysilicon layer, treating a surface of the polysilicon layer so that the surface of the polysilicon layer is electronegative, and supplying polar gas into a process chamber so that polar molecules of the polar gas are adsorbed on the surface of the polysilicon layer which is electronegative so as to form the polysilicon thin film, a surface of which has a hole density higher than an electron density.
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公开(公告)号：US10340354B2
公开(公告)日：2019-07-02
申请号：US15547643
申请日：2017-01-19
Inventor： Liangliang Li , Huibin Guo , Zheng Liu , Shoukun Wang , Yuchun Feng
IPC: H01L29/45 , H01L21/77 , H01L29/786 , H01L27/12 , H01L29/24 , H01L29/417 , G02F1/1368 , G02F1/1343
Abstract: A method of manufacturing a thin-film transistor (TFT) array substrate, including: forming a gate layer, a gate insulating layer, an oxide semiconductor layer, a source/drain electrode layer and a pixel electrode layer on a base substrate. The step of forming the source/drain electrode layer and the pixel electrode layer includes: forming a transparent conductive film and a first metallic film on the oxide semiconductor layer in sequence, to form a stack layer of the transparent conductive film and the first metallic film, in which the transparent conductive film contacts the oxide semiconductor layer; and forming source electrodes, drain electrodes and pixel electrodes by a single patterning process on the stack layer of the transparent conductive film and the first metallic film. One patterning process is saved, the production time is shortened, and the production cost is reduced.
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Patent Agency Ranking
公开(公告)号：US10325938B2
公开(公告)日：2019-06-18
申请号：US15531154
申请日：2016-06-06
Applicant: BOE Technology Group Co., Ltd.
Inventor： Zheng Liu
IPC: H01L27/12 , H01L29/786 , H01L21/265 , H01L21/02 , H01L21/266 , H01L29/66 , G02F1/1368 , H01L27/32
Abstract: A TFT array substrate, a method for manufacturing the same, and a display device including such TFT array substrate are disclosed. The TFT array substrate includes a base substrate (100); and two thin film transistors located on the base substrate. The two thin film transistors each includes an active layer (102, 107) having a source region and a drain region, the two active layers of the two thin film transistors are superposed with each other in a direction perpendicular to the base substrate. The drain region of one of the two active layers is electrically connected to the source region of the other one of the two active layers so that the two thin film transistors are connected in series.
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117.发明申请公开(公告)号：US20180107314A1
公开(公告)日：2018-04-19
申请号：US15678045
申请日：2017-08-15
Inventor： Benlian Wang , Zheng Liu
IPC: G06F3/041
CPC classification number: G06F3/0412 , G06F3/0416 , G06F3/044 , G06F2203/04103
Abstract: Embodiments of this disclosure relate to a touch control substrate and a manufacturing method thereof, a touch control display panel, and a display apparatus. This touch control substrate comprises: a base substrate; and a patterned touch control electrode layer provided on the base substrate, wherein the surface of the patterned touch control electrode layer departing from the side of the base substrate comprises a roughened surface.
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118.发明申请公开(公告)号：US20170271171A1
公开(公告)日：2017-09-21
申请号：US15321537
申请日：2016-03-07
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Xiaoyong Lu , Chunping Long , Chien Hung Liu , Yucheng Chan , Xiaolong Li , Zheng Liu
IPC: H01L21/321 , H01L21/3213 , H01L21/02
CPC classification number: H01L21/3212 , B81C2201/0121 , H01L21/02164 , H01L21/0217 , H01L21/02274 , H01L21/30625 , H01L21/31051 , H01L21/31053 , H01L21/32115 , H01L21/32134 , H01L21/32139 , H01L21/48 , H01L21/7684
Abstract: Embodiments of the present invention provide a method of processing a surface of a polysilicon and a method of processing a surface of a substrate assembly. The method of processing a surface of a polysilicon includes forming a material film on the surface of the polysilicon; and processing, by using a chemico-mechanical polishing technology, the surface of the polysilicon on which the material film is formed. The material film is selected such that the polysilicon is preferentially removed in a polishing process.
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公开(公告)号：US09721979B1
公开(公告)日：2017-08-01
申请号：US15106052
申请日：2016-01-14
Inventor： Zheng Liu , Tsung Chieh Kuo , Xi Chen , Xiaoxiang Zhang , Zhichao Zhang , Mingxuan Liu
IPC: H01L21/00 , H01L21/84 , G02F1/1343 , H01L27/12 , H01L29/66 , G02F1/1368 , G02F1/1333
CPC classification number: H01L27/1288 , G02F1/133345 , G02F1/134309 , G02F1/13439 , G02F1/136227 , G02F1/1368 , G02F2001/134318 , G02F2001/134372 , G02F2201/121 , G02F2201/123 , H01L21/77 , H01L27/12 , H01L29/66765
Abstract: A method for manufacturing an array substrate comprises: forming a pixel electrode and a gate of a thin film transistor on a substrate; forming a gate insulating layer; forming an active layer and a source and a drain, which are provided on the active layer, of the thin film transistor by a patterning process; forming a passivation layer; forming a main via penetrating through the gate insulating layer and the passivation layer and a main-via extension portion under a portion of the drain by a patterning process, wherein the main via is connected to the main-via extension portion; removing a portion of the drain which protrudes above the main-via extension portion so as to form a final via; and forming a connection electrode and a common electrode, wherein the connection electrode electrically connects the drain to the pixel electrode through the final via.
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120.发明授权公开(公告)号：US09673333B2
公开(公告)日：2017-06-06
申请号：US15122066
申请日：2016-02-22
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Zheng Liu , Xiaoyong Lu , Xiaolong Li , Yu-Cheng Chan
IPC: H01L29/786 , H01L27/02 , H01L27/12
CPC classification number: H01L29/78621 , H01L27/02 , H01L27/1222 , H01L27/124 , H01L27/1255 , H01L27/127 , H01L27/1288 , H01L29/66757 , H01L29/786 , H01L29/78645 , H01L29/78675 , H01L29/78696
Abstract: A method for fabricating a Polysilicon Thin-Film Transistor is provided. The method includes forming a polysilicon active layer, forming a first gate insulation layer and a first gate electrode sequentially on the active layer, conducting a first ion implantation process on the active layer by using the first gate electrode as a mask to form two doped regions at ends of the active layer, forming a second gate insulation layer and a second gate electrode sequentially on the first gate insulation layer and the first gate electrode, and conducting a second ion implantation process on the active layer by using the second gate electrode as another mask to form two source/drain implantation regions at two outer sides of the doped regions of the active layer. Accordingly, impurity concentration of the two doped regions is smaller than that of the two source/drain implantation regions.
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