利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

158 条记录 (耗时 0.028 秒)

    Semiconductor-insulator-silicide capacitor
    111.
    发明授权
    Semiconductor-insulator-silicide capacitor 失效
    半导体绝缘体硅化物电容器

    公开(公告)号：US07479439B2

    公开(公告)日：2009-01-20

    申请号：US11737844

    申请日：2007-04-20

    申请人： Douglas D. Coolbaugh ,  Zhong-Xiang He ,  Robert M. Rassel ,  Richard J. Rassel ,  Stephen A. St Onge

    发明人： Douglas D. Coolbaugh ,  Zhong-Xiang He ,  Robert M. Rassel ,  Richard J. Rassel ,  Stephen A. St Onge

    IPC分类号： H01L21/8244

    CPC分类号： H01L29/94

    摘要： A semiconductor-insulator-silicide (SIS) capacitor is formed by depositing a thin silicon containing layer on a salicide mask dielectric layer, followed by lithographic patterning of the stack and metallization of the thin silicon containing layer and other exposed semiconductor portions of a semiconductor substrate. The thin silicon containing layer is fully reacted during metallization and consequently converted to a silicide alloy layer, which is a first electrode of a capacitor. The salicide mask dielectric layer is the capacitor dielectric. The second electrode of the capacitor may be a doped polycrystalline silicon containing layer, a doped single crystalline semiconductor region, or another doped polycrystalline silicon containing layer disposed on the doped polycrystalline silicon containing layer. The SIS insulator may further comprise other dielectric layers and conductive layers to increase capacitance per area.

    摘要翻译： 半导体绝缘体硅化物（SIS）电容器是通过在硅化物掩模介电层上沉积薄硅层而形成的，随后叠层的平版印刷图案化以及薄硅层和半导体衬底的其它暴露的半导体部分的金属化 。 含硅薄层在金属化期间完全反应，因此转化为硅化物合金层，其是电容器的第一电极。 硅化物掩模介电层是电容器电介质。 电容器的第二电极可以是掺杂的多晶硅含硅层，掺杂的单晶半导体区域或设置在掺杂的多晶硅含硅层上的另一掺杂的多晶硅含硅层。 SIS绝缘体还可以包括其它电介质层和导电层，以增加每面积的电容。

    Resistor tuning
    113.
    发明授权
    Resistor tuning 有权
    电阻调谐

    公开(公告)号：US07239006B2

    公开(公告)日：2007-07-03

    申请号：US10709115

    申请日：2004-04-14

    申请人： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Robert M. Rassel ,  Anthony K. Stamper

    发明人： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Robert M. Rassel ,  Anthony K. Stamper

    IPC分类号： H01L29/00

    CPC分类号： H01C17/267

    摘要： A structure for resistors and the method for tuning the same. The resistor comprises an electrically conducting region coupled to a liner region. Both the electrically conducting region and the liner region are electrically coupled to first and second contact regions. A voltage difference is applied between the first and second contact regions. As a result, a current flows between the first and second contact regions in the electrically conducting region. The voltage difference and the materials of the electrically conducting region and the liner region are such that electromigration occurs only in the electrically conducting region. As a result, a void region within the electrically conducting region expands in the direction of the flow of the charged particles constituting the current. Because the resistor loses a conducting portion of the electrically conducting region to the void region, the resistance of the resistor is increased (i.e., tuned).

    摘要翻译： 电阻器结构及其调谐方法。 电阻器包括耦合到衬垫区域的导电区域。 导电区域和衬里区域都电耦合到第一和第二接触区域。 在第一和第二接触区域之间施加电压差。 结果，电流在导电区域中的第一和第二接触区域之间流动。 导电区域和衬垫区域的电压差和材料使得电迁移仅在导电区域中发生。 结果，导电区域内的空隙区域在构成电流的带电粒子的流动方向上膨胀。 因为电阻器将导电区域的导电部分损失到空隙区域，电阻器的电阻增加（即调谐）。

    Precision polysilicon resistor process
    114.
    发明授权
    Precision polysilicon resistor process 有权
    精密多晶硅电阻工艺

    公开(公告)号：US07112535B2

    公开(公告)日：2006-09-26

    申请号：US10605439

    申请日：2003-09-30

    申请人： Douglas D. Coolbaugh ,  Heidi L. Greer ,  Robert M. Rassel

    发明人： Douglas D. Coolbaugh ,  Heidi L. Greer ,  Robert M. Rassel

    IPC分类号： H01L21/302

    CPC分类号： H01L27/0738 ,  H01L27/0802 ,  H01L28/20

    摘要： A process is disclosed for fabricating precision polysilicon resistors which more precisely control the tolerance of the sheet resistivity of the produced polysilicon resistors. The process generally includes performing an emitter/FET activation rapid thermal anneal (RTA) on a wafer having partially formed polysilicon resistors, followed by steps of depositing a protective dielectric layer on the polysilicon, implanting a dopant through the protective dielectric layer into the polysilicon to define the resistance of the polysilicon resistors, and forming a silicide.

    摘要翻译： 公开了一种制造精密多晶硅电阻器的方法，其更精确地控制所产生的多晶硅电阻器的薄层电阻率的公差。 该方法通常包括在具有部分形成的多晶硅电阻器的晶片上执行发射极/ FET激活快速热退火（RTA），随后是在多晶硅上沉积保护性介电层的步骤，将掺杂剂通过保护电介质层注入到多晶硅中 限定多晶硅电阻器的电阻，并形成硅化物。

    Lateral hyperabrupt junction varactor diode in an SOI substrate
    116.
    发明授权
    Lateral hyperabrupt junction varactor diode in an SOI substrate 有权
    SOI衬底中的横向超破坏结变容二极管

    公开(公告)号：US08492843B2

    公开(公告)日：2013-07-23

    申请号：US13449419

    申请日：2012-04-18

    申请人： Jeffrey B. Johnson ,  Alvin J. Joseph ,  Robert M. Rassel ,  Yun Shi

    发明人： Jeffrey B. Johnson ,  Alvin J. Joseph ,  Robert M. Rassel ,  Yun Shi

    IPC分类号： H01L29/786

    CPC分类号： H01L29/93 ,  H01L29/7391

    摘要： A varactor diode includes a portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate and a gate electrode located thereupon. A first electrode having a doping of a first conductivity type laterally abuts a doped semiconductor region having the first conductivity type, which laterally abuts a second electrode having a doping of a second conductivity type, which is the opposite of the first conductivity type. A hyperabrupt junction is formed between the second doped semiconductor region and the second electrode. The gate electrode controls the depletion of the first and second doped semiconductor regions, thereby varying the capacitance of the varactor diode. A design structure for the varactor diode is also provided.

    摘要翻译： 变容二极管包括绝缘体上半导体（SOI）衬底的顶部半导体层的一部分和位于其上的栅电极。 具有第一导电类型的掺杂的第一电极横向邻接具有第一导电类型的掺杂半导体区域，其横向邻接具有与第一导电类型相反的第二导电类型的掺杂的第二电极。 在第二掺杂半导体区域和第二电极之间形成超破坏结。 栅电极控制第一和第二掺杂半导体区的耗尽，从而改变变容二极管的电容。 还提供了变容二极管的设计结构。

    Asymmetric junction field effect transistor
    119.
    发明授权
    Asymmetric junction field effect transistor 有权
    非对称结场效应晶体管

    公开(公告)号：US08169007B2

    公开(公告)日：2012-05-01

    申请号：US13037485

    申请日：2011-03-01

    申请人： Frederick G. Anderson ,  David S. Collins ,  Richard A. Phelps ,  Robert M. Rassel ,  Michael J. Zierak

    发明人： Frederick G. Anderson ,  David S. Collins ,  Richard A. Phelps ,  Robert M. Rassel ,  Michael J. Zierak

    IPC分类号： H01L29/00 ,  H01L29/76

    CPC分类号： H01L29/1058 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0843 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/20 ,  H01L29/22 ,  H01L29/66901 ,  H01L29/808

    摘要： A junction field effect transistor (JFET) in a semiconductor substrate includes a source region, a drain region, a channel region, an upper gate region, and a lower gate region. The lower gate region is electrically connected to the upper gate region. The upper and lower gate regions control the current flow through the channel region. By performing an ion implantation step that extends the thickness of the source region to a depth greater than the thickness of the drain region, an asymmetric JFET is formed. The extension of depth of the source region relative to the depth of the drain region reduces the length for minority charge carriers to travel through the channel region, reduces the on-resistance of the JFET, and increases the on-current of the JFET, thereby enhancing the overall performance of the JFET without decreasing the allowable Vds or dramatically increasing Voff/Vpinch.

    摘要翻译： 半导体衬底中的结型场效应晶体管（JFET）包括源极区，漏极区，沟道区，上部栅极区域和下部栅极区域。 下栅极区域电连接到上栅极区域。 上下栅极区域控制通过沟道区域的电流。 通过执行将源极区域的厚度延伸到大于漏极区域的厚度的深度的离子注入步骤，形成非对称JFET。 源极区域相对于漏极区域的深度的深度的扩展减小了少数电荷载流子穿过沟道区域的长度，减小了JFET的导通电阻，并增加了JFET的导通电流，由此 提高JFET的整体性能，而不会降低容许的Vds或显着增加Voff / Vpinch。