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    PROGRAMMABLE SEMICONDUCTOR DEVICE
    112.
    发明申请
    PROGRAMMABLE SEMICONDUCTOR DEVICE 有权
    可编程半导体器件

    公开(公告)号：US20110032025A1

    公开(公告)日：2011-02-10

    申请号：US12911379

    申请日：2010-10-25

    申请人： William R. Tonti ,  Wayne S. Berry ,  John A. Fifield ,  William H. Guthrie ,  Richard S. Kontra

    发明人： William R. Tonti ,  Wayne S. Berry ,  John A. Fifield ,  William H. Guthrie ,  Richard S. Kontra

    IPC分类号： H01H37/76 ,  H01L21/768

    CPC分类号： G11C17/16 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A programmable device includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end (12a) is substantially wider than the second end (12b), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.

    摘要翻译： 可编程器件包括衬底（10）; 绝缘体（13）; 绝缘体上的细长半导体材料（12），具有第一和第二端的细长半导体材料和上表面S; 第一端部（12a）比第二端部（12b）大得多，金属材料设置在上表面上; 所述金属材料可响应于流过半导体材料和金属材料的电流I而沿着上表面物理迁移。

    Electrically programmable π-shaped fuse structures and design process therefore
    113.
    发明授权
    Electrically programmable π-shaped fuse structures and design process therefore 失效
    因此电气可编程和形状的熔断器结构和设计过程

    公开(公告)号：US07784009B2

    公开(公告)日：2010-08-24

    申请号：US11923833

    申请日：2007-10-25

    申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Jack A. Mandelman ,  William R. Tonti

    发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Jack A. Mandelman ,  William R. Tonti

    IPC分类号： G06F17/50

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Electrically programmable fuses for an integrated circuit and design structures thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and a second support, respectively, with the first support and the second support being spaced apart, and the fuse element bridging the distance between the first terminal portion over the first support and the second terminal portion over the second support. The fuse, first support and second support define a π-shaped structure in elevational cross-section through the fuse element. The first terminal portion, second terminal portion and fuse element are coplanar, with the fuse element residing above a void. The design structure for the fuse is embodied in a machine-readable medium for designing, manufacturing or testing a design of the fuse.

    摘要翻译： 提出了用于集成电路的电可编程保险丝及其设计结构，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。 第一端子部分和第二端子部分分别驻留在第一支撑件和第二支撑件上，第一支撑件和第二支撑件间隔开，并且熔丝元件将第一端子部分之间的距离跨越第一支撑件和 在第二支撑件上方的第二端子部分。 保险丝，第一支撑件和第二支撑件通过保险丝元件在垂直截面中限定了一个“形”结构。 第一端子部分，第二端子部分和熔丝元件是共面的，其中熔丝元件位于空隙之上。 保险丝的设计结构体现在用于设计，制造或测试保险丝设计的机器可读介质中。

    Method and structure to process thick and thin fins and variable fin to fin spacing
    114.
    发明授权
    Method and structure to process thick and thin fins and variable fin to fin spacing 有权
    处理厚薄翅片和可变翅片翅片间距的方法和结构

    公开(公告)号：US07763531B2

    公开(公告)日：2010-07-27

    申请号：US11846544

    申请日：2007-08-29

    申请人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Kiran V. Chatty ,  Robert J. Gauthler, Jr. ,  Jed H. Rankin ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Kiran V. Chatty ,  Robert J. Gauthler, Jr. ,  Jed H. Rankin ,  William R. Tonti

    IPC分类号： H01L21/425

    CPC分类号： B07C5/344 ,  G01R31/2831

    摘要： The disclosure describes an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FETs.

    摘要翻译： 本公开描述了在同一衬底上具有多个半导体鳍片的集成电路，其具有不同的宽度和可变间隔。 形成电路的方法包括使用不同类型的心轴的侧壁图像转印过程。 翅片厚度和翅片翅片间距由用于在心轴上形成氧化物侧壁的氧化工艺控制，更具体地，通过处理时间和使用固有的，氧化增强的和/或氧化抑制的心轴来控制。 翅片厚度也通过使用与氧化物侧壁结合或代替氧化物侧壁的侧壁间隔来控制。 具体地，单独的氧化物侧壁的图像，侧壁间隔物的图像和/或侧壁间隔物和氧化物侧壁的组合图像被转移到半导体层中以形成散热片。 可以使用具有不同厚度和可变间隔的散热片来形成单个多鳍FET。

    Methods of fabricating a device structure for use as a memory cell in a non-volatile random access memory
    115.
    发明授权
    Methods of fabricating a device structure for use as a memory cell in a non-volatile random access memory 失效
    制造用作非易失性随机存取存储器中的存储器单元的器件结构的方法

    公开(公告)号：US07700428B2

    公开(公告)日：2010-04-20

    申请号：US12117950

    申请日：2008-05-09

    申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7881 ,  H01L27/1203 ,  H01L29/66825

    摘要： Methods for fabricating a device structure for use as a memory cell in a non-volatile random access memory. The method includes forming first and second semiconductor bodies on the insulating layer that have a separated, juxtaposed relationship, doping the first semiconductor body to form a source and a drain, and partially removing the second semiconductor body to define a floating gate electrode adjacent to the channel of the first semiconductor body. The method further includes forming a first dielectric layer between the channel of the first semiconductor body and the floating gate electrode, forming a second dielectric layer on a top surface of the floating gate electrode, and forming a control gate electrode on the second dielectric layer that cooperates with the floating gate electrode to control carrier flow in the channel in the first semiconductor body.

    摘要翻译： 制造用作非易失性随机存取存储器中的存储单元的器件结构的方法。 该方法包括在绝缘层上形成具有分开且并置的关系的第一和第二半导体本体，掺杂第一半导体本体以形成源极和漏极，并且部分地移除第二半导体本体以限定邻近 第一半导体体的通道。 该方法还包括在第一半导体本体的沟道与浮栅之间形成第一电介质层，在浮置栅电极的顶表面上形成第二电介质层，在第二电介质层上形成控制栅电极， 与浮栅电极配合，以控制第一半导体体的沟道中的载流子流动。

    Methods For Forming Back-End-Of-Line Resistive Semiconductor Structures
    117.
    发明申请
    Methods For Forming Back-End-Of-Line Resistive Semiconductor Structures 有权
    形成后端电阻半导体结构的方法

    公开(公告)号：US20100041202A1

    公开(公告)日：2010-02-18

    申请号：US12191633

    申请日：2008-08-14

    申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Robert Robison ,  Yun Shi ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Robert Robison ,  Yun Shi ,  William R. Tonti

    IPC分类号： H01L21/02

    CPC分类号： H01L23/5228 ,  H01L21/76816 ,  H01L23/5226 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In one embodiment, a second metal line embedded in a second dielectric layer overlies a first metal line embedded in a first dielectric layer. A portion of the second dielectric layer overlying the first metal line is recessed employing a photoresist and the second metal line as an etch mask. A doped semiconductor spacer is formed within the recess to provide a resistive link between the first metal line and the second metal line. In another embodiment, a first metal line and a second metal line are embedded in a dielectric layer. An area of the dielectric layer laterally abutting the first and second metal lines is recessed employing a photoresist and the first and second metal lines as an etch mask. A doped semiconductor spacer is formed on sidewalls of the first and second metal lines, providing a resistive link between the first and second metal lines.

    摘要翻译： 在一个实施例中，嵌入在第二介电层中的第二金属线覆盖在嵌入第一介电层中的第一金属线上。 覆盖第一金属线的第二电介质层的一部分使用光致抗蚀剂凹陷，第二金属线作为蚀刻掩模。 在凹槽内形成掺杂半导体衬垫，以在第一金属线和第二金属线之间提供电阻连接。 在另一个实施例中，第一金属线和第二金属线嵌入在电介质层中。 使用光致抗蚀剂和第一和第二金属线作为蚀刻掩模来凹入与第一和第二金属线横向邻接的电介质层的区域。 掺杂半导体衬垫形成在第一和第二金属线的侧壁上，提供第一和第二金属线之间的电阻连接。

    METHOD FOR MONITORING PATTERNING INTEGRITY OF ETCHED OPENINGS AND FORMING CONDUCTIVE STRUCTURES WITH THE OPENINGS
    120.
    发明申请
    METHOD FOR MONITORING PATTERNING INTEGRITY OF ETCHED OPENINGS AND FORMING CONDUCTIVE STRUCTURES WITH THE OPENINGS 有权
    用于监测雕刻开口的完整性和形成具有开口的导电结构的方法

    公开(公告)号：US20090255818A1

    公开(公告)日：2009-10-15

    申请号：US12101329

    申请日：2008-04-11

    申请人： Veeraraghavan S. Basker ,  Toshiharu Furukawa ,  William R. Tonti

    发明人： Veeraraghavan S. Basker ,  Toshiharu Furukawa ,  William R. Tonti

    IPC分类号： H01L21/288

    CPC分类号： H01L21/76879 ,  C25D5/10 ,  C25D5/12 ,  C25D7/123 ,  C25D21/12 ,  H01L21/2885 ,  H01L21/76802 ,  H01L22/14 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed are embodiments of a method that both monitors patterning integrity of etched openings (i.e., ensures that lithographically patterned and etched openings are complete) and forms on-chip conductive structures (e.g., contacts, interconnects, fuses, anti-fuses, capacitors, etc.) within such openings. The method embodiments incorporate an electro-deposition process to provide both the means by which pattern integrity of etched openings can be monitored and also the metallization required for the formation of conductive structures within the openings. Specifically, during the electro-deposition process, electron flow is established by applying a current to the back side of the semiconductor wafer, thus, eliminating the need for a seed layer. Electron flow through the wafer and into the electroplating solution is then monitored and used as an indicator of electroplating in the etched openings and, thereby, as an indicator that the openings are completely etched.

    摘要翻译： 公开了一种方法的实施例，两者都监控图案化蚀刻开口的完整性（即，确保光刻图案和蚀刻的开口完整），并且形成片上导电结构（例如，触点，互连，熔断器，抗熔丝，电容器等） 。）在这样的开口内。 该方法实施例包括电沉积工艺，以提供能够监测蚀刻开口的图案完整性的装置以及在开口内形成导电结构所需的金属化。 具体地，在电沉积过程中，通过向半导体晶片的背面施加电流来建立电子流动，从而消除了种子层的需要。 然后监测通过晶片并进入电镀溶液的电子流，并将其用作蚀刻开口中的电镀的指示剂，从而作为开口被完全蚀刻的指示器。