公开(公告)号：US09269629B2

公开(公告)日：2016-02-23

申请号：US14528830

申请日：2014-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Shom Ponoth ,  Theodorus Eduardus Standaert ,  Tenko Yamashita

IPC: H01L21/76 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L27/088 ,  H01L27/12 ,  H01L21/02 ,  H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L27/02

CPC classification number: H01L21/823481 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02227 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/26506 ,  H01L21/26566 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/6681 ,  H01L29/78

Abstract: FinFET structures with dielectric fins and methods of fabrication are disclosed. A gas cluster ion beam (GCIB) tool is used to apply an ion beam to exposed fins, which converts the fins from a semiconductor material such as silicon, to a dielectric such as silicon nitride or silicon oxide. Unlike some prior art techniques, where some fins are removed prior to fin merging, in embodiments of the present invention, fins are not removed. Instead, semiconductor (silicon) fins are converted to dielectric (nitride/oxide) fins where it is desirable to have isolation between groups of fins that comprise various finFET devices on an integrated circuit (IC).

公开(公告)号：US20150380514A1

公开(公告)日：2015-12-31

申请号：US14314404

申请日：2014-06-25

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Steven J. Bentley ,  Michael J. Hargrove ,  Chia-Yu Chen ,  Ryan O. Jung ,  Sivanandha K. Kanakasabapathy ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7836

Abstract: Approaches for providing junction overlap control in a semiconductor device are provided. Specifically, at least one approach includes: providing a gate over a substrate; forming a set of junction extensions in a channel region adjacent the gate; forming a set of spacer layers along each of a set of sidewalls of the gate; removing the gate between the set of spacer layers to form an opening; removing, from within the opening, an exposed sacrificial spacer layer of the set of spacer layers, the exposed sacrificial spacer layer defining a junction extension overlap linear distance from the set of sidewalls of the gate; and forming a replacement gate electrode within the opening. This results in a highly scaled advanced transistor having precisely defined junction profiles and well-controlled gate overlap geometry achieved using extremely abrupt junctions whose surface position is defined using the set of spacer layers.

Abstract translation: 提供了在半导体器件中提供接合重叠控制的方法。 具体地，至少一种方法包括：在衬底上提供栅极; 在与栅极相邻的沟道区域中形成一组结延伸部分; 沿着栅极的一组侧壁中的每一个形成一组间隔层; 移除所述一组间隔层之间的栅极以形成开口; 从所述开口内去除所述一组间隔层的暴露的牺牲间隔层，所述暴露的牺牲间隔层限定结延伸部与所述栅极侧壁的所述一组侧壁重叠线性距离; 以及在所述开口内形成替换栅电极。 这导致具有精确限定的接合轮廓的高度缩放的先进晶体管，并且使用极其突出的接头实现良好控制的栅极重叠几何，其表面位置使用该组间隔层限定。

公开(公告)号：US09159633B2

公开(公告)日：2015-10-13

申请号：US14026172

申请日：2013-09-13

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Tenko Yamashita ,  Chun-Chen Yeh ,  Jin Cho ,  Hui Zang

IPC: H01L23/58 ,  H01L29/10 ,  H01L21/66 ,  H01L21/8234

CPC classification number: H01L22/14 ,  G03F7/70466 ,  H01L21/823431 ,  H01L22/10 ,  H01L22/12 ,  H01L22/34

Abstract: A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region and forming a first and second source/drain regions in the active area. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region. The method further includes determining if an overlay shift has occurred during the formation of the active area by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact.

Abstract translation: 提供了一种使用多重图案化光刻工艺（MPLP）形成具有测试宏的集成电路的方法。 该方法包括形成具有第一和第二栅极区的测试宏的有源区，并在有源区中形成第一和第二源极/漏极区。 该方法还包括形成连接到第一栅极区域的第一触点，连接到第二栅极区域的第二触点，连接到第一源极/漏极区域的第三触点和连接到源极/漏极区域的第四触点。 该方法还包括通过测试第一接触，第二接触，第三接触或第四接触中的一个或多个之间的短路来确定在形成有源区域期间是否发生覆盖偏移。

公开(公告)号：US11562906B2

公开(公告)日：2023-01-24

申请号：US16265784

申请日：2019-02-01

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Oleg Gluschenkov ,  Zuoguang Liu ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L21/285 ,  H01L29/08 ,  H01L29/24 ,  H01L29/267 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768

Abstract: Techniques for forming a metastable phosphorous P-doped silicon Si source drain contacts are provided. In one aspect, a method for forming n-type source and drain contacts includes the steps of: forming a transistor on a substrate; depositing a dielectric over the transistor; forming contact trenches in the dielectric that extend down to source and drain regions of the transistor; forming an epitaxial material in the contact trenches on the source and drain regions; implanting P into the epitaxial material to form an amorphous P-doped layer; and annealing the amorphous P-doped layer under conditions sufficient to form a crystalline P-doped layer having a homogenous phosphorous concentration that is greater than about 1.5×1021 atoms per cubic centimeter (at./cm3). Transistor devices are also provided utilizing the present P-doped Si source and drain contacts.

公开(公告)号：US10818599B2

公开(公告)日：2020-10-27

申请号：US16237685

申请日：2019-01-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hiroaki Niimi ,  Shariq Siddiqui ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L29/161 ,  H01L29/08 ,  H01L27/092 ,  H01L23/535 ,  H01L23/532 ,  H01L23/485 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/285 ,  H01L21/02 ,  H01L29/66 ,  H01L29/165

Abstract: An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill. A second device contact is in contact with at least one of the silicon containing source and drain region of the second semiconductor device including a material stack of a titanium oxide layer and a titanium layer. The second device contact may further include a second tungsten fill.

公开(公告)号：US20200066638A1

公开(公告)日：2020-02-27

申请号：US16668409

申请日：2019-10-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Takashi Ando ,  Hiroaki Niimi ,  Tenko Yamashita

IPC: H01L23/535 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/768 ,  H01L29/51 ,  H01L23/485 ,  H01L21/285

Abstract: A method of making a semiconductor device includes forming a first source/drain trench and a second source/drain trench over a first and second source/drain region, respectively; forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench; forming a first source/drain contact over the first source/drain region, the first source/drain contact including a first tri-layer contact disposed between the first silicon dioxide layer and a first conductive material; and forming a second source/drain contact over the second source/drain region, the second source/drain contact including a second tri-layer contact disposed between the second silicon dioxide layer and a second conductive material; wherein the first tri-layer contact includes a first metal oxide layer in contact with the first silicon dioxide layer, and the second tri-layer contact includes a second metal oxide layer in contact with the second silicon dioxide layer.

公开(公告)号：US20190181012A1

公开(公告)日：2019-06-13

申请号：US16265784

申请日：2019-02-01

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Oleg Gluschenkov ,  Zuoguang Liu ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L21/285 ,  H01L29/66 ,  H01L29/24 ,  H01L21/768 ,  H01L29/08 ,  H01L29/78 ,  H01L29/267

Abstract: Techniques for forming a metastable phosphorous P-doped silicon Si source drain contacts are provided. In one aspect, a method for forming n-type source and drain contacts includes the steps of: forming a transistor on a substrate; depositing a dielectric over the transistor; forming contact trenches in the dielectric that extend down to source and drain regions of the transistor; forming an epitaxial material in the contact trenches on the source and drain regions; implanting P into the epitaxial material to form an amorphous P-doped layer; and annealing the amorphous P-doped layer under conditions sufficient to form a crystalline P-doped layer having a homogenous phosphorous concentration that is greater than about 1.5×1021 atoms per cubic centimeter (at./cm3). Transistor devices are also provided utilizing the present P-doped Si source and drain contacts.

公开(公告)号：US10319731B2

公开(公告)日：2019-06-11

申请号：US15673548

申请日：2017-08-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Chun-Chen Yeh ,  Tenko Yamashita ,  Kangguo Cheng

IPC: H01L27/11556 ,  H01L27/11526 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/423 ,  H01L27/088 ,  H01L29/788

Abstract: The disclosure is directed to an integrated circuit structure and method of forming the same. The integrated circuit structure may include: a first device region including: a floating gate structure substantially surrounding a first fin that is over a substrate; a first bottom source/drain within the substrate, and beneath the first fin and the floating gate structure; a first top source/drain over the first fin and the floating gate structure; a first spacer substantially surrounding the first top source/drain and disposed over the floating gate structure; and a gate structure substantially surrounding and insulated from the floating gate structure, the gate structure being disposed over the substrate and having a height greater than a height of the floating gate.

公开(公告)号：US10297452B2

公开(公告)日：2019-05-21

申请号：US15712301

申请日：2017-09-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hui Zang ,  Kangguo Cheng ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: One illustrative method disclosed includes selectively forming sacrificial conductive source/drain cap structures on and in contact with first and second source/drain contact structures positioned on opposite sides of a gate of a transistor and removing and replacing the spaced-apart sacrificial conductive source/drain cap structures with first and second separate, laterally spaced-apart insulating source/drain cap structures that are positioned on the first and second source/drain contact structures. The method also includes forming a gate contact opening that extends through a space between the insulating source/drain cap structures and through the gate cap so as to expose a portion of the gate structure and forming a conductive gate contact structure (CB) that is conductively coupled to the gate structure.

公开(公告)号：US10158003B2

公开(公告)日：2018-12-18

申请号：US14824349

申请日：2015-08-12

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Zuoguang Liu ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L21/285 ,  H01L21/324 ,  H01L29/45 ,  H01L27/088 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267

Abstract: A method of making a semiconductor device includes forming a fin in a substrate; depositing a first spacer material to form a first spacer around the fin; depositing a second spacer material to form a second spacer over the first spacer; recessing the first spacer and the second spacer; removing the first spacer; and performing an epitaxial growth process to form epitaxial growth on an end of the fin, along a sidewall of the fin, and adjacent to the fin.