公开(公告)号：US06576993B2

公开(公告)日：2003-06-10

申请号：US10045825

申请日：2001-10-19

申请人： Salman Akram

发明人： Salman Akram

IPC分类号： H01L23498

CPC分类号： H01L24/06 ,  H01L23/3114 ,  H01L23/4951 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48799 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

摘要： Methods for forming substantially chip scale packages and the resulting structures. The methods comprise applying an adhesive on an active surface of a semiconductor chip to form a patterned adhesive layer on a portion of the active surface. A leadframe having leads with inner lead ends and outer lead ends is provided. The inner lead ends of the leads are aligned proximate to the adhesive-free area and the leads are attached to the adhesive layer on the active surface of the semiconductor chip. The outer lead ends are oriented to form a footprint which is not substantially larger than the dimensions of the semiconductor chip.

摘要翻译： 用于形成基本上芯片级封装和所得结构的方法。 所述方法包括在半导体芯片的有源表面上施加粘合剂以在有源表面的一部分上形成图案化的粘合剂层。 提供具有内引线端和外引线端的引线架。 引线的内引线端靠近无粘合剂区域排列，并且引线连接到半导体芯片的有源表面上的粘合剂层。 外部引线端部被定向以形成基本上不大于半导体芯片的尺寸的覆盖区域。

公开(公告)号：US06563215B1

公开(公告)日：2003-05-13

申请号：US09480027

申请日：2000-01-10

申请人： Salman Akram ,  Alan G. Wood

发明人： Salman Akram ,  Alan G. Wood

IPC分类号： H01L2940

CPC分类号： G01R1/06711 ,  G01R1/07314 ,  H01L23/13 ,  H01L23/498 ,  H01L23/49872 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

摘要： An interconnect for semiconductor components includes a substrate, and interconnect contacts on the substrate for electrically engaging component contacts on the components. The interconnect contacts include silicon carbide conductive layers, and conductors in electrical communication with the silicon carbide conductive layers. The silicon carbide conductive layers provides a wear resistant surface, and improved heat transfer between the component contacts and the interconnect contacts. The silicon carbide conductive layers can comprise doped silicon carbide, or alternately thermally oxidized silicon carbide. The interconnect can be configured for use with a testing apparatus for testing discrete components such as dice or chip scale packages, or alternately for use with a testing apparatus for testing wafer sized components, such as wafers, panels and boards. In addition, the interconnect can be configured for constructing semiconductor packages and electronic assemblies such as multi chip modules.

摘要翻译： 用于半导体部件的互连件包括衬底和衬底上的互连触点，用于电连接部件上的组件触点。 互连触点包括碳化硅导电层和与碳化硅导电层电连通的导体。 碳化硅导电层提供耐磨表面，并且改善部件触点和互连触点之间的热传递。 碳化硅导电层可以包括掺杂的碳化硅，或交替地热氧化的碳化硅。 互连可以被配置用于与用于测试分立元件（例如骰子或芯片尺寸封装）的测试设备一起使用，或者替代地与用于测试晶片尺寸的元件（例如晶片，面板和板）的测试设备一起使用。 此外，互连可以被配置用于构造半导体封装和诸如多芯片模块的电子组件。

公开(公告)号：US06544461B1

公开(公告)日：2003-04-08

申请号：US09677555

申请日：2000-10-02

申请人： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  John O. Jacobson ,  James M. Wark ,  Syed Sajid Ahmad

发明人： David R. Hembree ,  Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  Derek Gochnour ,  John O. Jacobson ,  James M. Wark ,  Syed Sajid Ahmad

IPC分类号： B29C4502

CPC分类号： G01R1/0483

摘要： A semiconductor carrier for testing semiconductor components, such as bare dice and chip scale packages, and a method for fabricating the carrier are provided. The carrier includes a molded plastic base, a lead frame, and an interconnect. The interconnect includes contacts for making temporary electrical connections with corresponding contacts (e.g., bond pads, solder balls) on the components. The carrier is fabricated by attaching the interconnect to the lead frame, and then molding the plastic base to the interconnect and lead frame. An alternate embodiment carrier includes a board to which multiple interconnects are molded or laminated. In addition, clip members retain the components on the board in electrical communication with the interconnects. A gasket may be used to protect the interconnect contacts during the molding step.

摘要翻译： 提供了用于测试半导体部件的半导体载体，例如裸芯片和芯片级封装，以及制造载体的方法。 载体包括模制塑料基底，引线框架和互连件。 互连件包括用于与组件上的相应触点（例如，接合焊盘，焊球）进行临时电连接的触点。 通过将互连件附接到引线框架，然后将塑料基底模制到互连和引线框架来制造载体。 替代实施例的载体包括多个互连件模制或层压的板。 另外，夹子构件保持电路板上与组件电连通的组件。 可以在模制步骤期间使用垫圈来保护互连触点。

公开(公告)号：US06509647B2

公开(公告)日：2003-01-21

申请号：US09733572

申请日：2000-12-08

申请人： Salman Akram ,  Alan G. Wood ,  Warren M. Farnworth

发明人： Salman Akram ,  Alan G. Wood ,  Warren M. Farnworth

IPC分类号： H01L2348

CPC分类号： H01L23/13 ,  G01R1/0466 ,  G01R1/0483 ,  H01L23/49827 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/8114 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/15174 ,  H05K3/325 ,  H05K3/326 ,  H01L2224/05599

摘要： The present invention is directed toward apparatus and methods of testing and assembling bumped die and bumped devices using an anisotropically conductive layer. In one embodiment, a semiconductor device comprises a bumped device having a plurality of conductive bumps formed thereon, a substrate having a plurality of contact pads distributed thereon and approximately aligned with the plurality of conductive bumps, and an anisotropically conductive layer disposed between and mechanically coupled to the bumped device and to the substrate. The anisotropically conductive layer electrically couples each of the conductive bumps with a corresponding one of the contact pads.

公开(公告)号：US06492738B2

公开(公告)日：2002-12-10

申请号：US09389862

申请日：1999-09-02

申请人： Salman Akram ,  Alan G. Wood ,  Warren M. Farnworth

发明人： Salman Akram ,  Alan G. Wood ,  Warren M. Farnworth

IPC分类号： H01L2348

CPC分类号： H01L23/13 ,  G01R1/0466 ,  G01R1/0483 ,  H01L23/49827 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/8114 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/15174 ,  H05K3/325 ,  H05K3/326 ,  H01L2224/05599

摘要： The present invention is directed toward apparatus and methods of testing and assembling bumped die and bumped devices using an anisotropically conductive layer. In one embodiment, a semiconductor device comprises a bumped device having a plurality of conductive bumps formed thereon, a substrate having a plurality of contact pads distributed thereon and approximately aligned with the plurality of conductive bumps, and an anisotropically conductive layer disposed between and mechanically coupled to the bumped device and to the substrate. The anisotropically conductive layer electrically couples each of the conductive bumps with a corresponding one of the contact pads. In another embodiment, an apparatus for testing a bumped device having a plurality of conductive bumps includes a substrate having a plurality of contact pads distributed thereon and substantially alignable with the plurality of conductive bumps, and an anisotropically conductive layer disposed on the first surface and engageable with the plurality of conductive bumps to electrically couple each of the conductive bumps with a corresponding one of the contact pads. Alternately, the test apparatus may also include an alignment device or a bumped device handler. In another embodiment, a method of testing a bumped device includes engaging a plurality of contact pads with an anisotropically conductive layer, engaging the plurality of conductive bumps with the anisotropically conductive layer substantially opposite from and in approximate alignment with the plurality of contact pads, forming a plurality of conductive paths through the anisotropically conductive layer so that each of the conductive bumps is electrically coupled to one of the contact pads, and applying test signals through at least some of the contact pads and the conductive paths to at least some of the conductive bumps.

公开(公告)号：US06478627B2

公开(公告)日：2002-11-12

申请号：US09876805

申请日：2001-06-07

申请人： Warren M. Farnworth ,  David J. Corisis ,  Salman Akram

发明人： Warren M. Farnworth ,  David J. Corisis ,  Salman Akram

IPC分类号： H01R2370

CPC分类号： H01L25/0657 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01R12/57 ,  H01R12/7082 ,  H01R12/721 ,  H01R12/856 ,  H01R13/24 ,  H01R13/514 ,  H05K7/023 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49153 ,  Y10T29/49169 ,  Y10T29/49204 ,  Y10T29/49222 ,  H01L2924/00

摘要： A modular bare die socket assembly for attaching a plurality of miniature semiconductor dice to a substrate. The socket assembly is comprised of a plurality of two-sided plates joined vertically in a horizontal stack, wherein each plate has a die socket for the removable insertion of a bare semiconductor die. A multi-layer interconnect lead tape has a plurality of lithographically formed leads bent on one end to form nodes for attachment to bond pads on the removably inserted semiconductor die, and having opposing ends connectable to the substrate.

摘要翻译： 一种用于将多个微型半导体管芯附接到衬底的模块裸露裸露插座组件。 插座组件由在水平叠层中垂直连接的多个双面板组成，其中每个板具有用于可裸插入裸半导体管芯的管芯插座。 多层互连引线带具有在一端弯曲的多个光刻形成的引线，以形成用于附接到可移除插入的半导体管芯上的接合焊盘并具有可连接到基板的相对端的节点。

公开(公告)号：US06472240B2

公开(公告)日：2002-10-29

申请号：US09835052

申请日：2001-04-13

申请人： Salman Akram ,  David R. Hembree

发明人： Salman Akram ,  David R. Hembree

IPC分类号： H01L2166

CPC分类号： G01K1/026 ,  H01L22/12 ,  H01L2224/48091 ,  H01L2224/48464 ,  H01L2224/8592 ,  H01L2924/15156 ,  H01L2924/00014

摘要： The present invention includes electronic device workpieces, methods of semiconductor processing and methods of sensing temperature of an electronic device workpiece. In one aspect, the invention provides an electronic device workpiece including: a substrate having a surface; a temperature sensing device borne by the substrate; and an electrical interconnect formed upon the surface of the substrate, the electrical interconnect being electrically coupled with the temperature sensing device. In another aspect, a method of sensing temperature of an electronic device workpiece includes: providing an electronic device workpiece; supporting a temperature sensing device using the electronic device workpiece; providing an electrical interconnect upon a surface of the electronic device workpiece; electrically coupling the electrical interconnect with the temperature sensing device; and sensing temperature of the electronic device workpiece using the temperature sensing device.

摘要翻译： 本发明包括电子设备工件，半导体处理方法和感测电子设备工件温度的方法。 一方面，本发明提供了一种电子设备工件，包括：具有表面的基板; 由基板承载的温度感测装置; 以及形成在所述基板的表面上的电互连，所述电互连件与所述温度感测装置电耦合。 另一方面，一种感测电子设备工件的温度的方法包括：提供电子设备工件; 支持使用电子设备工件的温度感测装置; 在所述电子设备工件的表面上提供电互连; 将电互连电气耦合到温度感测装置; 以及使用温度感测装置感测电子装置工件的温度。

公开(公告)号：US06469532B2

公开(公告)日：2002-10-22

申请号：US10068082

申请日：2002-02-06

申请人： Salman Akram ,  David R. Hembree ,  Alan G. Wood

发明人： Salman Akram ,  David R. Hembree ,  Alan G. Wood

IPC分类号： G01R3102

CPC分类号： G01R31/2886 ,  G01R1/0408

摘要： An interconnect apparatus for testing bare semiconductor dice comprises raised contact members on a semiconductive substrate. The contact members are covered with an insulation layer an a conductive cap connected by a conductive trace to a testing circuit. The trace is covered with coaxial layers of a silicon-containing insulation an a metal for shielding the trace from “crosstalk” and other interference. An apparatus for simultaneous testing of multiple dies on a wafer has thermal expansion characteristic matching those of the semiconductor die or wafer and provides clean signals.

摘要翻译： 用于测试裸半导体裸片的互连装置包括半导体衬底上的凸起接触构件。 接触构件被绝缘层覆盖，导电盖通过导电迹线连接到测试电路。 迹线覆盖有同轴层的硅含绝缘材料和金属，用于屏蔽“串扰”和其他干扰。 用于在晶片上同时测试多个管芯的装置具有与半导体管芯或晶片匹配的热膨胀特性，并提供干净的信号。

公开(公告)号：US06462399B1

公开(公告)日：2002-10-08

申请号：US09652880

申请日：2000-08-31

申请人： Salman Akram

发明人： Salman Akram

IPC分类号： H01L2906

CPC分类号： H01L24/81 ,  H01L23/13 ,  H01L24/48 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/10165 ,  H01L2224/13111 ,  H01L2224/16237 ,  H01L2224/48463 ,  H01L2224/81136 ,  H01L2224/8114 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A micromachined insulative carrier substrate preferably formed of silicon and a multi-chip module formed from the micromachined substrate. The micromachined substrate is fabricated by forming mesas across the surface of the substrate, forming an insulating layer on the substrate, and forming conductive traces on the insulating layer to route signals between semiconductor dice and/or to external circuitry. A variety of semiconductor dice and/or integrated circuitry-bearing wafer configurations (collectively, “semiconductor elements”) may be attached to the semiconductor substrate. Electrical contact between the carrier substrate and semiconductor element is achieved with conductive connectors formed on either the semiconductor element or the carrier substrate. The conductive connectors each preferably make contact with both a portion of the conductive trace extending down the sidewall of the mesa and a portion of the conductive trace on the substrate between the mesas to form a more effective bond. The present invention also includes a stacked configuration. After attachment of semiconductor elements, the carrier substrates can be stacked to form a high density stacked configuration.

摘要翻译： 优选由硅形成的微加工绝缘性载体基板和由微加工基板形成的多芯片模块。 通过在衬底的表面上形成台面来形成微加工衬底，在衬底上形成绝缘层，并在绝缘层上形成导电迹线以在半导体管芯和/或外部电路之间路由信号。 各种半导体晶片和/或集成电路承载晶片配置（统称为“半导体元件”）可以附接到半导体衬底。 通过形成在半导体元件或载体基板上的导电连接器实现载体​​基板和半导体元件之间的电接触。 导电连接器各自优选地与沿着台面的侧壁向下延伸的导电迹线的一部分和在台面之间的衬底上的导电迹线的一部分接触以形成更有效的键。 本发明还包括层叠结构。 在安装半导体元件之后，可以堆叠载体基板以形成高密度堆叠构造。

公开(公告)号：US06456100B1

公开(公告)日：2002-09-24

申请号：US09009169

申请日：1998-01-20

申请人： David R. Hembree ,  Salman Akram ,  Derek Gochnour

发明人： David R. Hembree ,  Salman Akram ,  Derek Gochnour

IPC分类号： G01R3102

CPC分类号： G01R1/0466 ,  Y10T29/49117 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49153 ,  Y10T29/53209 ,  Y10T29/5323

摘要： A spring element used in a temporary package for testing semiconductors is provided. The spring element is compressed so as to press the semiconductor, either in the form of a bare semiconductor die or as part of a package, against an interconnect structure. The spring element is configured so that it provides sufficient pressure to keep the contacts on the semiconductor in electrical contact with the interconnect structure. Material is added and/or removed from the spring element so that it has the desired modulus of elasticity. The shape of the spring element may also be varied to change the modulus of elasticity, the spring constant, and the force transfer capabilities of the spring element.

摘要翻译： 提供了用于测试半导体的临时封装中的弹簧元件。 弹簧元件被压缩以将半导体以裸半导体管芯的形式或作为封装的一部分压在互连结构上。 弹簧元件构造成使得其提供足够的压力以保持半导体上的触点与互连结构电接触。 向弹簧元件添加和/或移除材料，使其具有所需的弹性模量。 弹簧元件的形状也可以改变以改变弹性元件的弹性模量，弹簧常数和力传递能力。