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235 条记录 (耗时 0.056 秒)

    Method for aligning a wafer
    111.
    发明授权
    Method for aligning a wafer 失效
    对准晶片的方法

    公开(公告)号：US6063440A

    公开(公告)日：2000-05-16

    申请号：US893461

    申请日：1997-07-11

    申请人： Ling Chen ,  Joseph Yudovsky ,  Ying Yu ,  Lawrence C. Lei

    发明人： Ling Chen ,  Joseph Yudovsky ,  Ying Yu ,  Lawrence C. Lei

    IPC分类号： C23C14/50 ,  C23C16/44 ,  C23C16/458 ,  H01L21/02 ,  H01L21/205 ,  H01L21/68 ,  C23C16/00

    CPC分类号： C23C16/4585 ,  C23C16/44 ,  H01L21/68

    摘要： A method for aligning a wafer on a support member within a vacuum chamber includes increasing the pressure within the vacuum chamber to at least about 1 Torr before aligning the wafer. The wafer is introduced into the vacuum chamber on the support member, the pressure is increased to at least about one Torr, and the support member is lifted into a shadow ring that has a frustoconical inner cavity constructed to funnel the wafer to a centered, aligned position.

    摘要翻译： 在真空室内的支撑构件上对准晶片的方法包括在对准晶片之前将真空室内的压力增加至至少约1Torr。 将晶片引入到支撑构件上的真空室中，将压力增加至至少约1乇，并将支撑构件提升到阴影环中，阴影环具有构造成将晶圆漏斗到中心对准的截头圆锥形内腔 位置。

    Methods and apparatus for minimizing excess aluminum accumulation in CVD chambers
    112.
    发明授权
    Methods and apparatus for minimizing excess aluminum accumulation in CVD chambers 失效
    用于最小化CVD室中过多的铝积聚的方法和装置

    公开(公告)号：US5858464A

    公开(公告)日：1999-01-12

    申请号：US791131

    申请日：1997-02-13

    申请人： Karl Littau ,  Dashun S. Zhou ,  Alfred Mak ,  Ling Chen

    发明人： Karl Littau ,  Dashun S. Zhou ,  Alfred Mak ,  Ling Chen

    IPC分类号： C23C16/20 ,  C23C16/44 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L23/52

    CPC分类号： H01L21/28556 ,  C23C16/4401 ,  C23C16/4404

    摘要： A method and apparatus for minimizing excess aluminum deposition that can build up inside a substrate processing chamber during an aluminum CVD substrate processing operation. The method of the present invention periodically introduces nitrogen into the processing chamber after aluminum CVD processing of at least a single wafer in order to minimize unwanted aluminum accumulation in various parts of the chamber. According to one embodiment, the present invention provides a method of minimizing excess metal deposition inside a substrate processing chamber after a substrate processing operation. The method includes the steps of introducing a nitrogen-containing passivating gas into a chamber after the substrate processing operation, and maintaining at least a portion of the chamber at a second temperature during the introducing step thereby reducing excess metal build up within the chamber. In preferred embodiments, the method is performed after removal of the substrate from the processing chamber. In other preferred embodiments, the second temperature ranges from about 200.degree.-300.degree. C.

    摘要翻译： 一种用于最小化在铝CVD衬底处理操作期间可以在衬底处理室内形成的多余铝沉积的方法和装置。 本发明的方法在对至少一个晶片进行铝CVD处理之后，将氮气周期性地引入处理室中，以便最小化腔室各部分中不希望的铝积聚。 根据一个实施例，本发明提供一种在衬底处理操作之后使衬底处理室内的多余金属沉积最小化的方法。 该方法包括以下步骤：在基板处理操作之后将含氮钝化气体引入室中，并且在引入步骤期间将室的至少一部分保持在第二温度，从而减少室内过量的金属积聚。 在优选的实施方案中，在从处理室中除去基材之后进行该方法。 在其它优选实施方案中，第二温度范围为约200-300℃

    Select gate enhanced high density read-only-memory device
    113.
    发明授权
    Select gate enhanced high density read-only-memory device 失效
    选择门增强型高密度只读存储器件

    公开(公告)号：US5777919A

    公开(公告)日：1998-07-07

    申请号：US713741

    申请日：1996-09-13

    申请人： Wu Chi-Yung ,  Ling Chen ,  Tony Peng

    发明人： Wu Chi-Yung ,  Ling Chen ,  Tony Peng

    IPC分类号： G11C7/18 ,  G11C17/12 ,  H01L27/115 ,  G11C17/00

    CPC分类号： H01L27/115 ,  G11C17/126 ,  G11C7/18

    摘要： The present invention is related to an enhanced high density Read-Only-Memory (ROM) device with select gate. A thin oxide layer is deposited on the ROM cell matrix and it is extended to the select lines which is on the top and bottom side of the ROM cell matrix to form the select gate. The ROM cell matrix can be organized more flexible by using the buried layers to pick out the unwanted gates. The metal contact can be directly made in this extended region too. Thereafter it reduces the manufacturing cost and achieves a high speed and density and simple process device.

    摘要翻译： 本发明涉及具有选择门的增强型高密度只读存储器（ROM）器件。 在ROM单元矩阵上沉积薄的氧化物层，并将其延伸到位于ROM单元矩阵的顶部和底部的选择线以形成选择栅极。 通过使用埋层挑出不想要的栅极，ROM单元矩阵可以更灵活地组织起来。 金属接触可以直接在这个扩展区域制造。 此后，它降低了制造成本，并实现了高速度和密度以及简单的工艺装置。

    Self-aligned source/drain mask ROM memory cell using trench etched channel
    114.
    发明授权
    Self-aligned source/drain mask ROM memory cell using trench etched channel 失效
    自对准源/漏极掩模ROM存储单元使用槽蚀刻通道

    公开(公告)号：US5751040A

    公开(公告)日：1998-05-12

    申请号：US716809

    申请日：1996-09-16

    申请人： Ling Chen ,  Hung-Cheng Sung ,  Chi-Shiung Lo

    发明人： Ling Chen ,  Hung-Cheng Sung ,  Chi-Shiung Lo

    IPC分类号： H01L21/8246 ,  H01L27/112 ,  H01L27/02 ,  H01L27/10

    CPC分类号： H01L27/1128 ,  H01L27/112

    摘要： A device and a method are provided for manufacture of that semiconductor memory device on a silicon semiconductor substrate with a vertical channel. A dielectric layer pattern with openings through it is formed. Trenches are formed in the surface of the semiconductor substrate. The trenches have sidewalls. A spacer layer is formed on the surface of the device. The spacer layer is shaped to form spacers in the trenches on the sidewalls. Source/drain regions are formed by ion implanting ions to deposit dopant into the substrate. The device is annealed to form source/drain regions in the substrate. A dielectric layer is formed over the device. A conductive word-line is formed and patterned over the dielectric layer.

    摘要翻译： 提供了一种用于在具有垂直通道的硅半导体衬底上制造该半导体存储器件的装置和方法。 形成具有穿过其的开口的电介质层图案。 沟槽形成在半导体衬底的表面中。 沟槽有侧壁。 在装置的表面上形成间隔层。 间隔层被成形为在侧壁上的沟槽中形成间隔物。 源/漏区通过离子注入离子形成以将掺杂剂沉积到衬底中。 该器件退火以在衬底中形成源极/漏极区域。 在该器件上形成介电层。 在电介质层上形成并图案化导电字线。

    Method of making a non-volatile memory cell
    116.
    发明授权
    Method of making a non-volatile memory cell 失效
    制造非易失性存储单元的方法

    公开(公告)号：US5633185A

    公开(公告)日：1997-05-27

    申请号：US390775

    申请日：1995-02-17

    申请人： Tom Dang-Hsing Yiu ,  Fuchia Shone ,  Tien-Ler Lin ,  Ling Chen

    发明人： Tom Dang-Hsing Yiu ,  Fuchia Shone ,  Tien-Ler Lin ,  Ling Chen

    IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115

    CPC分类号： H01L27/11519 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521

    摘要： An improved contactless EPROM array, EPROM cell design, and method for fabricating the same is based on a unique drain-source-drain configuration, in which a single source diffusion is shared by two columns of transistors. An elongated first drain diffusion region, an elongated source diffusion region, and an elongated second drain diffusion region, are formed in a semi-conductor substrate along essentially parallel lines. Field oxide regions are grown on opposite sides of the first and second drain diffusion regions. Floating gates and control gate wordlines are formed orthogonal to the drain-source-drain structure to establish two columns of storage cells having a shared source region. The shared source region is coupled through a bottom block select transistor to a virtual ground terminal. Each drain diffusion region is coupled through a top block select transistor to global bitline. The cell structure uses two metal global bitlines which extend essentially parallel to the drain, source and drain diffusion regions, and a virtual ground conductor which couples a plurality of columns of transistors to a virtual ground terminal through a horizontal conductor, such as a buried diffusion line.

    摘要翻译： 改进的非接触式EPROM阵列，EPROM单元设计及其制造方法基于唯一的漏极 - 源极 - 漏极配置，其中单个源极扩散由两列晶体管共享。 沿着基本上平行的线，在半导体衬底中形成细长的第一漏极扩散区域，细长源极扩散区域和细长的第二漏极扩散区域。 场氧化物区域在第一和第二漏极扩散区域的相对侧上生长。 浮置栅极和控制栅极字线与漏极 - 源极 - 漏极结构正交形成，以建立具有共享源极区域的两列存储单元。 共享源极区域通过底部块选择晶体管耦合到虚拟接地端子。 每个漏极扩散区域通过顶部块选择晶体管耦合到全局位线。 电池结构使用两个基本平行于漏极，源极和漏极扩散区域延伸的金属全局位线，以及通过水平导体（例如埋入扩散）将多个晶体管列耦合到虚拟接地端子的虚拟接地导体 线。

    Process for manufacturing a plug-diode mask ROM
    117.
    发明授权
    Process for manufacturing a plug-diode mask ROM 失效
    用于制造插头二极管掩模ROM的工艺

    公开(公告)号：US5441907A

    公开(公告)日：1995-08-15

    申请号：US266505

    申请日：1994-06-27

    申请人： Hung-Cheng Sung ,  Ling Chen

    发明人： Hung-Cheng Sung ,  Ling Chen

    IPC分类号： H01L27/102 ,  H01L21/329

    CPC分类号： H01L27/1021

    摘要： A method of manufacture of a Mask ROM on a semiconductor substrate comprises formation of a first plurality of conductor lines in a first array. A dielectric layer is formed upon the device with a matrix of openings therein in line with the first array. The openings expose the surface of the first conductor lines. Semiconductor diodes are formed in the matrix of openings in contact with the first conductor lines. A second plurality of conductor lines are formed on the surface of the dielectric layer in a second array of conductor lines orthogonal to the first plurality of conductor lines in the first array. A second plurality of conductor lines is aligned with the matrix and is in contact with the upper ends of the semiconductor diodes.

    摘要翻译： 在半导体衬底上制造掩模ROM的方法包括以第一阵列形成第一多条导体线。 电介质层在其上具有与第一阵列一致的开口矩阵的器件上形成。 开口露出第一导体线的表面。 半导体二极管形成在与第一导线接触的开口矩阵中。 在与第一阵列中的第一多个导体线正交的导体线的第二阵列中，在电介质层的表面上形成第二多个导体线。 第二多个导体线与矩阵对准并且与半导体二极管的上端接触。

    Full-featured EEPROM
    118.
    发明授权
    Full-featured EEPROM 失效
    全功能EEPROM

    公开(公告)号：US5216268A

    公开(公告)日：1993-06-01

    申请号：US764013

    申请日：1991-09-23

    申请人： Ling Chen ,  Tien-ler Lin

    发明人： Ling Chen ,  Tien-ler Lin

    IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L29/788

    CPC分类号： H01L29/66825 ,  H01L29/7883 ,  H01L27/115

    摘要： Disclosed is a byte-erasable EEPROM memory cell which utilizes a five volt external source and a voltage multiplier circuit to program and erase a floating gate by means of electron tunneling. To prevent collapse of the voltage multiplier circuit a lightly doped drain region is incorporated preventing gate modulated junction breakdown, thereby preventing collapse of the voltage multiplier circuit. In addition, current flow through the channel separating a source region and the lightly doped drain region is controlled by a portion of a control gate and the floating gate, thereby allowing a higher erased cell threshold voltage. Also disclosed is a process for forming the lightly doped drain region by using the control gate as an effective sidewall spacer.

    摘要翻译： 公开了一种字节可擦除EEPROM存储单元，其利用五伏外部源和电压倍增器电路来通过电子隧道对浮动栅极进行编程和擦除。 为了防止电压倍增器电路的崩溃，掺入了轻掺杂的漏极区域，防止栅极调制结击穿，从而防止电压倍增器电路的崩溃。 此外，通过分离源极区域和轻掺杂漏极区域的沟道的电流流动由控制栅极和浮置栅极的一部分控制，从而允许更高的擦除单元阈值电压。 还公开了通过使用控制栅极作为有效侧壁间隔物来形成轻掺杂漏极区的工艺。

    DEVICES AND METHODS FOR FLOW CONTROL OF MESSAGES IN A PASSIVE OPTICAL NETWORK (PON) AND METHODS THEREIN
    120.
    发明申请
    DEVICES AND METHODS FOR FLOW CONTROL OF MESSAGES IN A PASSIVE OPTICAL NETWORK (PON) AND METHODS THEREIN 有权
    无源光网络（PON）中的信息流控制的装置和方法及其方法

    公开(公告)号：US20150188750A1

    公开(公告)日：2015-07-02

    申请号：US14409354

    申请日：2012-06-20

    申请人： Ling Chen ,  Laith Said

    发明人： Ling Chen ,  Laith Said

    IPC分类号： H04L12/24 ,  H04B10/27

    CPC分类号： H04B10/07 ,  H04B10/272 ,  H04B2210/071 ,  H04L41/06 ,  H04L41/0604 ,  H04L43/16 ,  H04L47/266 ,  H04Q11/0067 ,  H04Q2011/0088

    摘要： A method in an Optical Line Terminal (OLT) device for transmitting a flow control message to an Optical Network Unit/Terminal (ONU/T) device in a Passive Optical Network (PON) access network is provided. The OLT device is configured to receive alarm and/or Attribute Value Change (AVC) messages from the ONU/T device. The OLT device is also configured to temporarily store the alarm and/or AVC messages in a message queue. The OLT device generates a flow control message indicating that the ONU/T device is to stop transmitting alarm and/or AVC messages to the OLT device, when the number of alarm and/or AVC messages in the message queue exceeds a first threshold. Then, the OLT device transmits the flow control message to the ONU/T device(s). An OLT device for transmitting a flow control message to an ONU/T device, and an ONU/T device and related method for receiving a flow control message are also provided.

    摘要翻译： 提供了一种用于向无源光网络（PON）接入网络中的光网络单元/终端（ONU / T）设备发送流量控制消息的光线路终端（OLT）装置中的方法。 OLT设备被配置为从ONU / T设备接收报警和/或属性值改变（AVC）消息。 OLT设备还被配置为将报警和/或AVC消息临时存储在消息队列中。 当消息队列中的报警和/或AVC消息的数量超过第一阈值时，OLT设备生成指示ONU / T设备停止向OLT设备发送报警和/或AVC消息的流控制消息。 然后，OLT装置向ONU / T装置发送流量控制消息。 还提供了用于向ONU / T设备发送流控制消息的OLT设备，以及用于接收流控制消息的ONU / T设备及相关方法。