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公开(公告)号:US20230268018A1
公开(公告)日:2023-08-24
申请号:US17675477
申请日:2022-02-18
发明人: Vamsi Rayaprolu , Ashutosh Malshe , Gary Besinga , Roy Leonard
CPC分类号: G11C16/3495 , G11C16/102 , G11C16/16 , G11C16/26 , G11C16/32
摘要: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a data validity metric value with respect to a source set of memory cells of the memory device; determining whether the data validity metric value satisfies a first threshold criterion; responsive to determining that the data validity metric value satisfies the first threshold criterion, performing a data integrity check on the source set of memory cells to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a second threshold criterion; and responsive to determining that the data integrity metric value fails to satisfy the second threshold criterion, causing the memory device to copy data from the source set of memory cells to a destination set of memory cells of the memory device.
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公开(公告)号:US11721404B2
公开(公告)日:2023-08-08
申请号:US17484777
申请日:2021-09-24
发明人: Kishore K. Muchherla , Ashutosh Malshe , Preston A. Thomson , Michael G. Miller , Gary F. Besinga , Scott A. Stoller , Sampath K. Ratnam , Renato C. Padilla , Peter Feeley
CPC分类号: G11C16/349 , G11C16/12 , G11C2211/5641
摘要: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.
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公开(公告)号:US11709633B2
公开(公告)日:2023-07-25
申请号:US17685102
申请日:2022-03-02
发明人: Gianni Stephen Alsasua , Harish Reddy Singidi , Peter Sean Feeley , Ashutosh Malshe , Renato Padilla, Jr. , Kishore Kumar Muchherla , Sampath Ratnam
CPC分类号: G06F3/0659 , G06F3/064 , G06F3/0604 , G06F3/0679 , G11C16/3422
摘要: Systems and methods are disclosed, comprising a memory device comprising multiple groups of memory cells, the groups comprising a first group of memory cells and a second group of memory cells configured to store information at a same bit capacity per memory cell, and a processing device operably coupled to the memory device, the processing device configured to adjust a scan event threshold for one of the first or second groups of memory cells to a threshold less than a target scan event threshold for the first and second groups of memory cells to distribute scan events in time on the memory device.
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公开(公告)号:US20230153011A1
公开(公告)日:2023-05-18
申请号:US18098279
申请日:2023-01-18
CPC分类号: G06F3/0652 , G06F3/0608 , H03M7/6011 , G06F11/1004 , G06F3/0679
摘要: A processing device, operatively coupled with a memory device, is configured to perform a write operation on a page of a plurality of pages of a data unit of a memory device. The processing device further generates a parity page for data stored in the page of the data unit and associates the parity page with parity data associated with the data unit. Responsive to determining that a first size of the parity data is larger than a first threshold size, the processing device compresses the parity data. Responsive to determining that a second size of the compressed parity data is larger than a second threshold size, the processing device releases at least a subset of the parity data corresponding to a subset of the data that is free from defects.
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公开(公告)号:US20230141181A1
公开(公告)日:2023-05-11
申请号:US18093069
申请日:2023-01-04
IPC分类号: G06F3/06
CPC分类号: G06F3/0608 , G06F3/0679 , G06F3/0646
摘要: A method includes determining a respective number of and respective locations of valid data portions of a plurality of blocks of NAND memory cells, based on the respective locations of the valid data portions, determining respective dispersions of the valid data portions within the plurality of blocks of NAND memory cells, based at least on the respective dispersions, selecting a block of NAND memory cells from the plurality of blocks of NAND memory cells, and performing a folding operation on the selected block.
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公开(公告)号:US11635899B2
公开(公告)日:2023-04-25
申请号:US17573224
申请日:2022-01-11
发明人: Kulachet Tanpairoj , Sebastien Andre Jean , Kishore Kumar Muchherla , Ashutosh Malshe , Jianmin Huang
IPC分类号: G06F12/00 , G06F3/06 , G06F12/0811 , G06F12/02
摘要: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The SLC memory cells serve as a high-speed cache providing SLC level performance with the storage capacity of a memory device with MLC memory cells. The proportion of cells configured as MLC vs the proportion that are configured as SLC storage may be configurable, and in some examples, the proportion may change during usage based upon configurable rules based upon memory device metrics. In some examples, when the device activity is below an activity threshold, the memory device may skip the SLC cache and place the data directly into the MLC storage to reduce power consumption.
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公开(公告)号:US20230076362A1
公开(公告)日:2023-03-09
申请号:US17984929
申请日:2022-11-10
发明人: Michael G. Miller , Ashutosh Malshe , Gianni Stephen Alsasua , Renato Padilla, JR. , Vamsi Pavan Rayaprolu , Kishore Kumar Muchherla , Harish Reddy Singidi
摘要: A processing device detects a read operation at a memory device that is directed at a word line group from among multiple word line groups of the memory device. The processing device increments a read counter associated with the word line group based on the read operation being directed at the word line group. The processing device determines the read counter exceeds a read-disturb threshold and performs read-disturb handling on the word line group in response to determining the read counter exceeds the read-disturb threshold.
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公开(公告)号:US20230059923A1
公开(公告)日:2023-02-23
申请号:US17980234
申请日:2022-11-03
发明人: Vamsi Pavan Rayaprolu , Kishore Kumar Muchherla , Ashutosh Malshe , Gianni S. Alsasua , Harish R. Singidi
摘要: A trigger rate associated with a scan operation of a set of memory pages of a data block is identified. The trigger rate is compared to a threshold rate to determine that a condition is satisfied. In response to satisfying the condition, a refresh operation is executed on the set of memory pages of the data block.
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公开(公告)号:US20230057863A1
公开(公告)日:2023-02-23
申请号:US17981649
申请日:2022-11-07
IPC分类号: G06F3/06
摘要: A method includes determining that a ratio of valid data portions of a block of memory cells is greater than or less than a valid data portion threshold and performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions is greater than the valid data portion threshold. The method further includes performing a second media management operation on the block of memory cells in response to determining that the ratio of valid data portions is less than the valid data portion threshold.
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公开(公告)号:US11544188B2
公开(公告)日:2023-01-03
申请号:US17196934
申请日:2021-03-09
发明人: Yun Li , Kishore Kumar Muchherla , Peter Feeley , Ashutosh Malshe , Daniel J. Hubbard , Christopher S. Hale , Kevin R. Brandt , Sampath K. Ratnam
IPC分类号: G06F12/00 , G06F12/02 , G06F12/0891
摘要: Memory circuits including dynamically configurable cache cells are disclosed herein. The cache cells may be selectively and dynamically configured to select one or more bits per cell according to a real-time determination or characterization of a workload type.
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