公开(公告)号：US20250124962A1

公开(公告)日：2025-04-17

申请号：US19002110

申请日：2024-12-26

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC: G11C11/405 ,  G11C16/04 ,  H10B12/00 ,  H10B41/20 ,  H10B41/70 ,  H10B69/00 ,  H10D30/60 ,  H10D30/67 ,  H10D62/40 ,  H10D62/80 ,  H10D62/83 ,  H10D84/03 ,  H10D84/90 ,  H10D86/40 ,  H10D86/60 ,  H10D87/00 ,  H10D88/00

Abstract: An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

公开(公告)号：US20250123483A1

公开(公告)日：2025-04-17

申请号：US18985601

申请日：2024-12-18

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Yosuke TSUKAMOTO ,  Kiyoshi KATO ,  Tatsuya ONUKI ,  Yoshiaki OIKAWA ,  Kensuke YOSHIZUMI

IPC: G02B27/00 ,  G02B27/01

Abstract: Provided is a multifunctional display device or a multifunctional electronic device. Provided is a display device or electronic device with high visibility. Provided is a display device or electronic device with low power consumption. The electronic device includes a housing, a display device, a system unit, a camera, a secondary battery, a reflective surface, and a wearing tool. The system unit and the secondary battery are each positioned inside the housing. The system unit includes a charging circuit unit. The charging circuit unit is configured to control charging of the secondary battery. The system unit is configured to perform first processing based on imaging data of the camera. The first processing includes at least one of gesture operation, head tracking, and eye tracking. The system unit is configured to generate image data based on the first processing. The display device is configured to display the image data.

公开(公告)号：US20250120181A1

公开(公告)日：2025-04-10

申请号：US18982263

申请日：2024-12-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka SHIONOIRI ,  Hiroyuki MIYAKE ,  Kiyoshi KATO

IPC: H10D86/80 ,  G11C16/04 ,  H10B41/70 ,  H10B69/00 ,  H10D30/67 ,  H10D86/40 ,  H10D86/60

Abstract: It is an object to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory device. As a switching element for holding electric charge accumulated in a transistor which functions as a memory element, a transistor including an oxide semiconductor film as an active layer is provided for each memory cell in the memory device. The transistor which is used as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.

公开(公告)号：US20250056786A1

公开(公告)日：2025-02-13

申请号：US18723731

申请日：2022-12-15

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Ryota HODO ,  Tatsuya ONUKI ,  Kiyoshi KATO

IPC: H10B12/00

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a transistor and a capacitor; the transistor includes an oxide, a first conductor and a second conductor over the oxide, a first insulator that is placed over the first conductor and the second conductor and includes a first opening and a second opening, a second insulator in the first opening of the first insulator, and a third conductor over the second insulator; the first opening in the first insulator includes a region overlapping with the oxide; the third conductor includes a region overlapping with the oxide with the second insulator therebetween; the capacitor includes the second conductor, a third insulator in the second opening of the first insulator, and a fourth conductor over the third insulator; and the distance between the first conductor and the second conductor is smaller than the width of the first opening in a cross-sectional view of the transistor in a channel length direction.

公开(公告)号：US20250008721A1

公开(公告)日：2025-01-02

申请号：US18706096

申请日：2022-10-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Hitoshi KUNITAKE ,  Rihito WADA ,  Kiyoshi KATO ,  Tatsuya ONUKI

IPC: H10B12/00

Abstract: A small semiconductor device is provided. The semiconductor device includes a first layer and a second layer over the first layer. The first layer includes a p-channel first transistor containing silicon in a channel formation region. The second layer includes an n-channel second transistor containing a metal oxide in a channel formation region. The first transistor and the second transistor form a CMOS circuit. A channel length of the first transistor is longer than a channel length of the second transistor.

公开(公告)号：US20240402994A1

公开(公告)日：2024-12-05

申请号：US18683540

申请日：2022-09-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi KATO ,  Tatsuya ONUKI ,  Atsushi MIYAGUCHI ,  Yoshiaki OIKAWA ,  Shunpei YAMAZAKI

IPC: G06F7/523 ,  G06F7/50 ,  G11C11/405 ,  H10B12/00

Abstract: An electronic device with a novel structure is provided. In an electronic device including a semiconductor device, the semiconductor device includes a CPU, an accelerator, and a memory device. The CPU includes a scan flip-flop circuit and a backup circuit electrically connected to the scan flip-flop circuit. The backup circuit includes a first transistor. The accelerator includes an arithmetic circuit and a data retention circuit electrically connected to the arithmetic circuit. The data retention circuit includes a second transistor. The memory device includes a memory cell including a third transistor. The first transistor to the third transistor each include a semiconductor layer containing a metal oxide in a channel formation region.

公开(公告)号：US20240284674A1

公开(公告)日：2024-08-22

申请号：US18586866

申请日：2024-02-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hajime KIMURA ,  Takanori MATSUZAKI ,  Kiyoshi KATO ,  Satoru OKAMOTO

IPC: H10B43/27 ,  H01L29/24 ,  H01L29/51 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

CPC classification number: H10B43/27 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50 ,  H01L29/24 ,  H01L29/513

Abstract: A semiconductor device with a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening, a first conductor that is over the first insulator and includes a second opening, a second insulator that is over the first insulator and includes a third opening, and an oxide penetrating the first opening, the second opening, and the third opening. The oxide includes a first region at least in the first opening, a second region at least in the second opening, and a third region at least in the third opening. The resistances of the first region and the third region are lower than the resistance of the second region.

公开(公告)号：US20230397447A1

公开(公告)日：2023-12-07

申请号：US18235995

申请日：2023-08-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC: H10B99/00 ,  H01L27/12 ,  H01L29/24 ,  H01L29/16 ,  G11C11/405 ,  G11C16/04 ,  H01L27/105 ,  H01L27/118 ,  H10B41/20 ,  H10B41/70 ,  H10B69/00 ,  H01L29/786

CPC classification number: H10B99/00 ,  H01L27/1207 ,  H01L29/24 ,  H01L29/16 ,  G11C11/405 ,  G11C16/0433 ,  H01L27/105 ,  H01L27/11803 ,  H01L27/1225 ,  H10B41/20 ,  H10B41/70 ,  H10B69/00 ,  H01L29/7869 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/247 ,  H01L29/78693 ,  H01L29/78696 ,  G11C2211/4016 ,  H01L21/8221

Abstract: An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

公开(公告)号：US20230369342A1

公开(公告)日：2023-11-16

申请号：US18224224

申请日：2023-07-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi KATO ,  Masayuki SAKAKURA

IPC: H01L27/12 ,  H01L29/786 ,  H10B12/00

CPC classification number: H01L27/1225 ,  H01L29/7869 ,  H01L27/1255 ,  H10B12/30

Abstract: A semiconductor device that is suitable for miniaturization and higher density is provided. A semiconductor device includes a first transistor over a semiconductor substrate, a second transistor including an oxide semiconductor over the first transistor, and a capacitor over the second transistor. The capacitor includes a first conductor, a second conductor, and an insulator. The second conductor covers a side surface of the first conductor with an insulator provided therebetween.

公开(公告)号：US20230335180A1

公开(公告)日：2023-10-19

申请号：US18206117

申请日：2023-06-06

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Takahiko ISHIZU ,  Tatsuya ONUKI

IPC: G11C11/408 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786 ,  H10B99/00

CPC classification number: G11C11/4085 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/78648 ,  H01L29/7869 ,  H10B99/00

Abstract: A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.