公开(公告)号：US11217478B2

公开(公告)日：2022-01-04

申请号：US16600826

申请日：2019-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Kuan-Chieh Huang

IPC: H01L21/768 ,  H01L27/088 ,  H01L21/762 ,  H01L23/522 ,  H01L23/48 ,  H01L27/06 ,  H01L21/822 ,  H01L23/525

Abstract: An integrated circuit (IC) provides high performance and high functional density. A first back-end-of-line (BEOL) interconnect structure and a second BEOL interconnect structure are respectively under and over a semiconductor substrate. A first electronic device and a second electronic device are between the semiconductor substrate and respectively a bottom of the first BEOL interconnect structure and a top of the second BEOL interconnect structure. A through substrate via (TSV) extends through the semiconductor substrate, from the first BEOL interconnect structure to the second BEOL interconnect structure. A method for manufacturing the IC is also provided.

公开(公告)号：US11107767B2

公开(公告)日：2021-08-31

申请号：US16710271

申请日：2019-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Hsun-Ying Huang

IPC: H01L23/538 ,  H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L21/683 ,  H01L23/31 ,  H01L23/528 ,  H01L23/525

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first plurality of interconnect layers within a first inter-level dielectric (ILD) structure disposed along a front-side of a first substrate. A conductive pad is arranged along a back-side of the first substrate and a first through-substrate-via (TSV) extends between an interconnect wire of the first plurality of interconnect layers and the conductive pad. A second plurality of interconnect layers are within a second ILD structure disposed along a front-side of a second substrate that is bonded to the first substrate. A second through substrate via (TSV) extends through the second substrate. The second TSV has a greater width than the first TSV.

公开(公告)号：US20210151495A1

公开(公告)日：2021-05-20

申请号：US16684871

申请日：2019-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chiang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Jhy-Jyi Sze ,  Shyh-Fann Ting ,  Yimin Huang

IPC: H01L27/146

Abstract: The problem of reducing noise in image sensing devices, especially NIR detectors, is solved by providing ground connections for the reflectors. The reflectors may be grounded through vias that couple the reflectors to grounded areas of the substrate. The grounded areas of the substrate may be P+ doped areas formed proximate the surface of the substrate. In particular, the P+ doped areas may be parts of photodiodes. Alternatively, the reflectors may be grounded through a metal interconnect structure formed over the front side of the substrate.

公开(公告)号：US10797091B2

公开(公告)日：2020-10-06

申请号：US16113101

申请日：2018-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Seiji Takahashi ,  Chen-Jong Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Feng-Jia Shiu ,  Jen-Cheng Liu ,  Jhy-Jyi Sze ,  Chun-Wei Chang ,  Wei-Cheng Hsu ,  Wei Chuang Wu ,  Yimin Huang

IPC: H01L27/146

Abstract: In some embodiments, a pixel sensor is provided. The pixel sensor includes a first photodetector arranged in a semiconductor substrate. A second photodetector is arranged in the semiconductor substrate, where a first substantially straight line axis intersects a center point of the first photodetector and a center point of the second photodetector. A floating diffusion node is arranged in the semiconductor substrate at a point that is a substantially equal distance from the first photodetector and the second photodetector. A pick-up well contact region is arranged in the semiconductor substrate, where a second substantially straight line axis that is substantially perpendicular to the first substantially straight line axis intersects a center point of the floating diffusion node and a center point of the pick-up well contact region.

公开(公告)号：US10790265B2

公开(公告)日：2020-09-29

申请号：US15846831

申请日：2017-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Jeng-Shyan Lin ,  Hsun-Ying Huang

IPC: H01L25/065 ,  H01L23/48 ,  H01L29/10 ,  H01L21/768 ,  H01L21/324 ,  H01L21/265

Abstract: A semiconductor device structure is provided. The semiconductor device structure has a first surface and a second surface. A first charged layer is disposed over the second surface. A dielectric layer separates a surface of the first charged layer that is closest to the semiconductor substrate from the second surface of the semiconductor substrate. A second charged layer is over the first charged layer. The first charged layer and the second charged layer are different materials and have a same charge polarity.

公开(公告)号：US20200035672A1

公开(公告)日：2020-01-30

申请号：US16578299

申请日：2019-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kong-Beng Thei ,  Dun-Nian Yaung ,  Fu-Jier Fan ,  Hsing-Chih Lin ,  Hsiao-Chin Tuan ,  Jen-Cheng Liu ,  Alexander Kalnitsky ,  Yi-Sheng Chen

IPC: H01L27/06 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L23/522 ,  H01L23/48

Abstract: A three-dimensional (3D) integrated circuit (IC) and associated forming method are provided. In some embodiments, a second IC die is bonded to a first IC die through a second bonding structure and a first bonding structure at a bonding interface. The bonding encloses a seal-ring structure in a peripheral region of the 3D IC in the first and second IC dies. The seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate. The bonding forms a plurality of through silicon via (TSV) coupling structures at the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure by electrically and correspondingly connects a first plurality of TSV wiring layers and inter-wire vias and a second plurality of TSV wiring layers and inter-wire vias.

公开(公告)号：US10515994B2

公开(公告)日：2019-12-24

申请号：US16148141

申请日：2018-10-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Chuang ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Tzu-Hsuan Hsu ,  Feng-Chi Hung ,  Min-Feng Kao

IPC: H01L27/146

Abstract: Semiconductor devices, methods of manufacturing thereof, and image sensor devices are disclosed. In some embodiments, a semiconductor device comprises a semiconductor chip comprising an array region, a periphery region, and a through-via disposed therein. The semiconductor device comprises a guard structure disposed in the semiconductor chip between the array region and the through-via or between the through-via and a portion of the periphery region.

公开(公告)号：US20190165009A1

公开(公告)日：2019-05-30

申请号：US15822701

申请日：2017-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Chuang Wu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Jen-Cheng Liu ,  Yen-Ting Chiang ,  Chun-Yuan Chen ,  Shen-Hui Hong

IPC: H01L27/146 ,  H04N5/369 ,  H04N5/374

Abstract: The present disclosure relates to a CMOS image sensor having a multiple deep trench isolation (MDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within a substrate and respectively comprising a photodiode. A boundary deep trench isolation (BDTI) structure is disposed between adjacent pixel regions, extending from a back-side of the substrate to a first depth within the substrate, and surrounding the photodiode. A multiple deep trench isolation (MDTI) structure is disposed within the individual pixel region, extending from the back-side of the substrate to a second depth within the substrate, and overlying the photodiode. A dielectric layer fills in a BDTI trench of the BDTI structure and a MDTI trench of the MDTI structure.

公开(公告)号：US10290671B2

公开(公告)日：2019-05-14

申请号：US15714043

申请日：2017-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-De Wang ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Chun-Chieh Chuang ,  Jeng-Shyan Lin

IPC: H01L27/14 ,  H01L27/146 ,  H01L23/48

Abstract: An image sensor device includes a first substrate, an interconnect structure, a conductive layer, a conductive via and a second substrate. The first substrate includes a first region including a pixel array and a second region including a circuit. The interconnect structure is over the pixel array or the circuit. The interconnect structure electrically connecting the circuit to the pixel array. The conductive layer is on the interconnect structure. The conductive via passes through the second substrate and at least partially embedded in the conductive layer. The second substrate is over the conductive layer.

公开(公告)号：US10276622B2

公开(公告)日：2019-04-30

申请号：US15718061

申请日：2017-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-I Hsu ,  Feng-Chi Hung ,  Chun-Chieh Chuang ,  Dun-Nian Yaung ,  Jen-Cheng Liu

IPC: H01L27/146

Abstract: An image-sensor device includes a substrate including a pixel region and a logic region. A logic transistor is disposed in the logic region and is surrounded by a logic isolation feature. A radiation-sensing region is disposed in the pixel region of the substrate. An epitaxial pixel isolation feature is disposed in the pixel region and surrounds the radiation-sensing region. A doped region with a same doping polarity as the radiation-sensing region is located between a bottom of the radiation-sensing region and the back surface of the substrate. The epitaxial pixel isolation feature is in direct contact with the doped region. The doped region extends continuously under the pixel region and the logic region. The epitaxial pixel isolation feature is in direct contact with the doped region, and the logic isolation feature is spaced apart from the doped region.