公开(公告)号：US11824007B2

公开(公告)日：2023-11-21

申请号：US17690206

申请日：2022-03-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Po-Yao Chuang ,  Meng-Liang Lin ,  Yi-Wen Wu ,  Shin-Puu Jeng ,  Techi Wong

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/5384 ,  H01L21/4885 ,  H01L21/56 ,  H01L21/76802 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/14

Abstract: A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.

公开(公告)号：US20230369164A1

公开(公告)日：2023-11-16

申请号：US18360484

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Chen Lee ,  Shu-Shen Yeh ,  Chia-Kuei Hsu ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/373 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L23/367 ,  H01L23/31

CPC classification number: H01L23/3735 ,  H01L23/49838 ,  H01L25/0655 ,  H01L24/73 ,  H01L23/49833 ,  H01L23/3675 ,  H01L23/49822 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/16 ,  H01L2924/16251 ,  H01L2224/16238 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/182

Abstract: A semiconductor structure includes: a substrate; a package attached to a first surface of the substrate, where the package includes: an interposer, where a first side of the interposer is bonded to the first surface of the substrate through first conductive bumps; dies attached to a second side of the interposer opposing the first side; and a molding material on the second side of the interposer around the dies; a plurality of thermal interface material (TIM) films on a first surface of the package distal from the substrate, where each of the TIM films is disposed directly over at least one respective die of the dies; and a heat-dissipation lid attached to the first surface of the substrate, where the package and the plurality of TIM films are disposed in an enclosed space between the heat-dissipation lid and the substrate, where the heat-dissipation lid contacts the plurality of TIM films.

公开(公告)号：US20230274999A1

公开(公告)日：2023-08-31

申请号：US18312877

申请日：2023-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Chin-Hua Wang ,  Chia-Kuei Hsu ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L23/3675 ,  H01L25/0655 ,  H01L24/16 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49822 ,  H01L21/4857 ,  H01L21/4871 ,  H01L21/563 ,  H01L21/565 ,  H01L25/50 ,  H01L21/4853 ,  H01L2224/16227

Abstract: Semiconductor devices and methods of manufacture which utilize lids in order to constrain thermal expansion during annealing are presented. In some embodiments lids are placed and attached on encapsulant and, in some embodiments, over first semiconductor dies. As such, when heat is applied, and the encapsulant attempts to expand, the lid will work to constrain the expansion, reducing the amount of stress that would otherwise accumulate within the encapsulant.

公开(公告)号：US11728233B2

公开(公告)日：2023-08-15

申请号：US16941847

申请日：2020-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Po-Yao Lin ,  Shin-Puu Jeng ,  Po-Chen Lai ,  Kuang-Chun Lee ,  Che-Chia Yang ,  Chin-Hua Wang ,  Yi-Hang Lin

IPC: H01L23/24 ,  H01L23/498 ,  H01L25/18 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L23/24 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/15311

Abstract: A method for forming a chip package structure is provided. The method includes disposing a first chip structure and a second chip structure over a wiring substrate. The first chip structure is spaced apart from the second chip structure by a gap. The method includes disposing a ring structure over the wiring substrate. The ring structure has a first opening, the first chip structure and the second chip structure are in the first opening, the first opening has a first inner wall, the first inner wall has a first recess, and the gap extends toward the first recess.

公开(公告)号：US20230207531A1

公开(公告)日：2023-06-29

申请号：US18175189

申请日：2023-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Shin-Puu Jeng ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Cheng-Chieh Hsieh ,  Ming-Yen Chiu

IPC: H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L25/10 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L25/0657 ,  H01L23/49816 ,  H01L21/568 ,  H01L25/105 ,  H01L23/3677 ,  H01L23/49838 ,  H01L23/49811 ,  H01L23/3128 ,  H01L23/3675 ,  H01L21/4853 ,  H01L2225/06548 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2924/181 ,  H01L2924/15311 ,  H01L2224/80904 ,  H01L24/03

Abstract: A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.

公开(公告)号：US11682599B2

公开(公告)日：2023-06-20

申请号：US16199535

申请日：2018-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Techi Wong ,  Meng-Wei Chou ,  Meng-Liang Lin ,  Po-Yao Chuang ,  Shin-Puu Jeng

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L23/3114 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/5389

Abstract: A method for forming a chip package structure is provided. The method includes disposing a chip over a redistribution structure. The method includes forming a molding layer over the redistribution structure and adjacent to the chip. The method includes partially removing the molding layer to form a trench in the molding layer, and the trench is spaced apart from the chip.

公开(公告)号：US11610854B2

公开(公告)日：2023-03-21

申请号：US17222044

申请日：2021-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Po-Yao Chuang ,  Ming-Chih Yew ,  Shin-Puu Jeng

IPC: H01L23/66 ,  H01Q1/22 ,  H01Q9/28 ,  H01Q9/04 ,  H01L21/56 ,  H01L23/00 ,  H01L23/48 ,  H01L23/31

Abstract: A device includes a redistribution structure, a first semiconductor device, a first antenna, and a first conductive pillar on the redistribution structure that are electrically connected to the redistribution structure, an antenna structure over the first semiconductor device, wherein the antenna structure includes a second antenna that is different from the first antenna, wherein the antenna structure includes an external connection bonded to the first conductive pillar, and a molding material extending between the antenna structure and the redistribution structure, the molding material surrounding the first semiconductor device, the first antenna, the external connection, and the first conductive pillar.

公开(公告)号：US11594520B2

公开(公告)日：2023-02-28

申请号：US17073953

申请日：2020-10-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Shin-Puu Jeng ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Cheng-Chieh Hsieh ,  Ming-Yen Chiu

IPC: H01L23/34 ,  H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L25/10 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L25/16

Abstract: A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.

公开(公告)号：US20220384313A1

公开(公告)日：2022-12-01

申请号：US17818729

申请日：2022-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Che-Chia Yang ,  Chin-Hua Wang ,  Po-Yao Lin ,  Shin-Puu Jeng ,  Chia-Hsiang Lin

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

公开(公告)号：US20220384304A1

公开(公告)日：2022-12-01

申请号：US17370591

申请日：2021-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Chen Lee ,  Shu-Shen Yeh ,  Chia-Kuei Hsu ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/373 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor structure includes: a substrate; a package attached to a first surface of the substrate, where the package includes: an interposer, where a first side of the interposer is bonded to the first surface of the substrate through first conductive bumps; dies attached to a second side of the interposer opposing the first side; and a molding material on the second side of the interposer around the dies; a plurality of thermal interface material (TIM) films on a first surface of the package distal from the substrate, where each of the TIM films is disposed directly over at least one respective die of the dies; and a heat-dissipation lid attached to the first surface of the substrate, where the package and the plurality of TIM films are disposed in an enclosed space between the heat-dissipation lid and the substrate, where the heat-dissipation lid contacts the plurality of TIM films.