公开(公告)号：US20250113566A1

公开(公告)日：2025-04-03

申请号：US18479580

申请日：2023-10-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ting Chen ,  Tai-Jung Kuo ,  Mu-Chieh Chang ,  Zhen-Cheng Wu ,  Sung-En Lin ,  Tze-Liang Lee

IPC: H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Various embodiments include protection layers for a transistor and methods of forming the same. In an embodiment, a method includes: exposing a semiconductor nanostructure, a dummy nanostructure, and an isolation region by removing a dummy gate; increasing a deposition selectivity between a top surface of the semiconductor nanostructure and a top surface of the isolation region relative a selective deposition process; depositing a protection layer on the top surface of the isolation region by performing the selective deposition process; removing the dummy nanostructure by selectively etching a dummy material of the dummy nanostructure at a faster rate than a protection material of the protection layer; and forming a gate structure around the semiconductor nanostructure.

公开(公告)号：US12211766B2

公开(公告)日：2025-01-28

申请号：US17657184

申请日：2022-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Jen Sung ,  Jr-Hung Li ,  Tze-Liang Lee

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/538 ,  H01L25/10

Abstract: A method includes bonding a first wafer to a second wafer, performing a trimming process on the first wafer, and depositing a sidewall protection layer contacting a sidewall of the first wafer. The depositing the sidewall protection layer includes depositing a high-density material in contact with the sidewall of the first wafer. The sidewall protection layer has a density higher than a density of silicon oxide. The method further includes removing a horizontal portion of the sidewall protection layer that overlaps the first wafer, and forming an interconnect structure over the first wafer. The interconnect structure is electrically connected to integrated circuit devices in the first wafer.

公开(公告)号：US20240387729A1

公开(公告)日：2024-11-21

申请号：US18775341

申请日：2024-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Han-Chi Lin ,  Chunyao Wang ,  Ching Yu Huang ,  Tze-Liang Lee ,  Yung-Chih Wang

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/3115 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

Abstract: A method includes etching a first portion and a second portion of a dummy gate stack to form a first opening and a second opening, respectively, and depositing a silicon nitride layer to fill the first opening and the second opening. The deposition of the silicon nitride layer comprises a first process selected from treating the silicon nitride layer using hydrogen radicals, implanting the silicon nitride layer, and combinations thereof. The method further includes etching a third portion of the dummy gate stack to form a trench, etching a semiconductor fin underlying the third portion to extend the trench down into a bulk portion of a semiconductor substrate underlying the dummy gate stack, and depositing a second silicon nitride layer into the trench.

公开(公告)号：US20240379815A1

公开(公告)日：2024-11-14

申请号：US18783885

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bor Chiuan Hsieh ,  Tsai-Jung Ho ,  Po-Cheng Shih ,  Tze-Liang Lee

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming gate spacers on opposing sides of the dummy gate stack, forming a source/drain region on a side of the dummy gate stack, forming an inter-layer dielectric over the source/drain region, replacing the dummy gate stack with a replacement gate stack, recessing the replacement gate stack to form a recess between the gate spacers, depositing a liner extending into the recess, depositing a masking layer over the liner and extending into the recess, forming an etching mask covering a portion of the masking layer, and etching the inter-layer dielectric to form a source/drain contact opening. The source/drain region is underlying and exposed to the source/drain contact opening. A source/drain contact plug is formed in the source/drain contact opening. A gate contact plug extends between the gate spacers and electrically connecting to the replacement gate stack.

公开(公告)号：US20240304496A1

公开(公告)日：2024-09-12

申请号：US18668960

申请日：2024-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Tai-Chun Huang ,  Jr-Hung Li ,  Tze-Liang Lee ,  Chi On Chui

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545

Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. The isolation regions extend into a semiconductor substrate. A portion of the semiconductor fin is etched to form a trench, which extends lower than bottom surfaces of the isolation regions, and extends into the semiconductor substrate. The method further includes filling the trench with a first dielectric material to form a first fin isolation region, recessing the first fin isolation region to form a first recess, and filling the first recess with a second dielectric material. The first dielectric material and the second dielectric material in combination form a second fin isolation region.

公开(公告)号：US20240249942A1

公开(公告)日：2024-07-25

申请号：US18595554

申请日：2024-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Yu Chang ,  Jung-Hau Shiu ,  Jen Hung Wang ,  Tze-Liang Lee

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/0331 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02214 ,  H01L21/0228 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32139

Abstract: A method for manufacturing an integrated circuit includes patterning a plurality of photomask layers over a substrate, partially backfilling the patterned plurality of photomask layers with a first material using atomic layer deposition, completely backfilling the patterned plurality of photomask layers with a second material using atomic layer deposition, removing the plurality of photomask layers to form a masking structure comprising at least one of the first and second materials, and transferring a pattern formed by the masking structure to the substrate and removing the masking structure. The first material includes a silicon dioxide, silicon carbide, or carbon material, and the second material includes a metal oxide or metal nitride material.

公开(公告)号：US20240112905A1

公开(公告)日：2024-04-04

申请号：US18525473

申请日：2023-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Yu Chang ,  Jei Ming Chen ,  Tze-Liang Lee

IPC: H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/768

CPC classification number: H01L21/02274 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/76802

Abstract: A method of forming a semiconductor device includes forming a mask layer over a substrate and forming an opening in the mask layer. A gap-filling material is deposited in the opening. A plasma treatment is performed on the gap-filling material. The height of the gap-filling material is reduced. The mask layer is removed. The substrate is patterned using the gap-filling material as a mask.

公开(公告)号：US20230387228A1

公开(公告)日：2023-11-30

申请号：US18366469

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Chou ,  Jr-Hung Li ,  Tze-Liang Lee

IPC: H01L29/417 ,  H01L23/535 ,  H01L29/40 ,  H01L29/78 ,  H01L21/768

CPC classification number: H01L29/41791 ,  H01L23/535 ,  H01L29/401 ,  H01L29/7851 ,  H01L21/76897 ,  H01L21/76832

Abstract: A semiconductor device a method of forming the same are provided. A semiconductor device includes a gate stack over a substrate. A first dielectric layer is over the gate stack. The first dielectric layer includes a first material. A second dielectric layer is over the first dielectric layer. The second dielectric layer includes a second material different from the first material. A first conductive feature is adjacent the gate stack. A second conductive feature is over and in physical contact with a topmost surface of the first conductive feature. A bottommost surface of the second conductive feature is in physical contact with a topmost surface of the second dielectric layer.

公开(公告)号：US20230386848A1

公开(公告)日：2023-11-30

申请号：US18230712

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Chou ,  Tze-Liang Lee

IPC: H01L21/28 ,  H01L21/768 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L21/28247 ,  H01L21/76816 ,  H01L21/76802 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/401 ,  H01L21/31116

Abstract: A method includes forming a dummy gate stack on a semiconductor fin, forming gate spacers on sidewalls of the dummy gate stack, forming a first inter-layer dielectric, with the gate spacers and the dummy gate stack being in the first inter-layer dielectric, removing the dummy gate stack to form a trench between the gate spacers, forming a replacement gate stack in the trench, and depositing a dielectric capping layer. A bottom surface of the dielectric capping layer contacts a first top surface of the replacement gate stack and a second top surface of the first inter-layer dielectric. A second inter-layer dielectric is deposited over the dielectric capping layer. A source/drain contact plug is formed and extends into the second inter-layer dielectric, the dielectric capping layer, and the first inter-layer dielectric.

公开(公告)号：US20230335436A1

公开(公告)日：2023-10-19

申请号：US17720899

申请日：2022-04-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ren Wang ,  Jen Hung Wang ,  Tze-Liang Lee

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76832 ,  H01L23/5329 ,  H01L23/5226

Abstract: A semiconductor device includes a first conductive feature, a first dielectric layer over the first conductive feature, a second conductive feature extending through the first dielectric layer, an air gap between the first dielectric layer and the second conductive feature, and an etch stop layer over the second conductive feature and the first dielectric layer. The etch stop layer covers the air gap, and the air gap extends above a bottommost surface of the etch stop layer.