公开(公告)号：US20170229345A1

公开(公告)日：2017-08-10

申请号：US15016230

申请日：2016-02-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/7681 ,  H01L21/76813 ,  H01L21/76816 ,  H01L2221/1021

Abstract: A substrate having thereon a first dielectric layer, a second dielectric layer, and a hard mask layer is provided. A partial via is formed in the second dielectric layer and the hard mask layer. A first photoresist pattern with a first trench opening above the partial via and a second trench opening is formed on the hard mask layer. The hard mask layer and the second dielectric layer are etched through the first trench opening and the second trench opening, thereby forming a first dual damascene structure comprising a first trench and a first via, and a second trench in the second dielectric layer, respectively. A second photoresist pattern having a self-aligned via opening above the second trench is formed. The second dielectric layer is etched through the self-aligned via opening, thereby forming a second dual damascene structure comprising the second trench and a second via under the second trench.

公开(公告)号：US09673049B2

公开(公告)日：2017-06-06

申请号：US14683120

申请日：2015-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/308

CPC classification number: H01L21/0337 ,  H01L21/3086

Abstract: A manufacturing method of a patterned structure of a semiconductor device includes following steps. A plurality of support features are formed on a substrate. A first conformal spacer layer is formed on the support features and a surface of the substrate, a second conformal spacer layer is formed on the first conformal spacer layer, and a covering layer is formed on the second conformal spacer layer. A gap between the support features is filled with the first conformal spacer layer, the second conformal spacer layer, and the covering layer. A first process is performed to remove a part of the covering layer, the second conformal spacer layer, and the first conformal spacer layer. A second process is performed to remove the support features or the first conformal spacer layer between the support feature and the second conformal spacer layer to expose a part of the surface of the substrate.

公开(公告)号：US20170141221A1

公开(公告)日：2017-05-18

申请号：US14981869

申请日：2015-12-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/768 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L29/785 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795

Abstract: A FinFET is provided. The FinFET includes a substrate. A plurality of fin structures are defined on the substrate. A gate structure crosses each fin structure. Two first recesses are disposed on two sides of the gate structure respectively, wherein each first recess further includes a plurality of second recesses disposed therein, and the position of each second recess corresponds to each fin structure. Two epitaxial layers are disposed at two sides of the gate structure respectively and in the first recesses, each epitaxial layer has a bottom surface including a second concave and convex profile, and each epitaxial layer directly contacts a bottom surface of each first recess and a bottom surface of each second recess.

公开(公告)号：US20170139329A1

公开(公告)日：2017-05-18

申请号：US14940108

申请日：2015-11-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chia-Hung Wang

IPC: G03F7/20 ,  G01B11/27

CPC classification number: G03F7/70141 ,  G01B11/272 ,  G03F7/70633

Abstract: A semiconductor processing method is provided and includes the following steps. A first semiconductor process is performed for a wafer to obtain plural overlay datum (x, y), wherein x and y are respectively shift values in X-direction and Y-direction. Next, A re-correct process is performed by a computer, wherein the re-correct process comprises: (a) providing an overlay tolerance value (A, B) and an original out of specification value (OOS %), wherein A and B are respectively predetermined tolerance values in X-direction and Y-direction; (b) providing at least a k value (kx, ky); (c) modifying the overlay datum (x, y) according to the k value (kx, ky) to obtain at least a revised overlay datum (x′, y′) ; and (d) calculating a process parameter from the revised overlay datum (x′, y′). Lastly, a second semiconductor process is performed according to the process parameter . . . . The present invention further provides a lithography system.

公开(公告)号：US09614061B2

公开(公告)日：2017-04-04

申请号：US15188998

申请日：2016-06-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/417 ,  H01L21/285 ,  H01L21/768 ,  H01L29/165 ,  H01L29/267 ,  H01L29/161 ,  H01L29/24

CPC classification number: H01L29/6681 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/823431 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/7856 ,  H01L2029/7858

Abstract: A semiconductor device includes: a substrate, a fin-shaped structure on the substrate, and a dummy fin-shaped structure on the substrate and adjacent to the fin-shaped structure. Preferably, the fin-shaped structure includes a gate structure thereon and a first epitaxial layer adjacent to two sides of the gate structure, and the dummy fin-shaped structure includes a second epitaxial layer thereon. A contact plug is disposed on the first epitaxial layer and the second epitaxial layer. In addition, the dummy fin-shaped structure includes a curve, in which the curve is omega shaped.

公开(公告)号：US20170069540A1

公开(公告)日：2017-03-09

申请号：US15356671

申请日：2016-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/10 ,  H01L27/088 ,  H01L29/08 ,  H01L29/06 ,  H01L21/324

CPC classification number: H01L21/823431 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02667 ,  H01L21/324 ,  H01L21/3247 ,  H01L21/823412 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: The present invention provides a method for forming a semiconductor structure. Firstly, a substrate is provided, the substrate comprises an insulating layer and at least one first nano channel structure disposed thereon, a first region and a second region being defined on the substrate, next, a hard mask is formed within the first region, afterwards, an etching process is performed, to remove parts of the insulating layer within the second region, an epitaxial process is then performed, to form an epitaxial layer on the first nano channel structure, and an anneal process is performed, to transform the first nano channel structure and the epitaxial layer into a first nanowire structure, wherein the diameter of the first nanowire structure within the first region is different from the diameter of the first nanowire structure within the second region.

Abstract translation: 本发明提供一种形成半导体结构的方法。 首先，提供基板，所述基板包括绝缘层和设置在其上的至少一个第一纳米通道结构，在所述基板上限定第一区域和第二区域，接下来，在所述第一区域内形成硬掩模 执行蚀刻处理，以去除第二区域内的绝缘层的部分，然后进行外延工艺，以在第一纳米通道结构上形成外延层，并进行退火工艺以将第一纳米管 沟道结构和外延层形成第一纳米线结构，其中第一区域内的第一纳米线结构的直径不同于第二区域内的第一纳米线结构的直径。

公开(公告)号：US20170025540A1

公开(公告)日：2017-01-26

申请号：US14841628

申请日：2015-08-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Tang-Chun Weng ,  Chien-Hao Chen

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a plurality of fin shaped structures, a trench, a spacing layer and a dummy gate structure. The fin shaped structures are disposed on a substrate. The trench is disposed between the fin shaped structures. The spacing layer is disposed on sidewalls of the trench, wherein the spacing layer has a top surface lower than a top surface of the fin shaped structures. The dummy gate structure is disposed on the fin shaped structures and across the trench.

Abstract translation: 半导体器件及其制造方法，半导体器件包括多个鳍状结构，沟槽，间隔层和虚拟栅极结构。 鳍状结构设置在基板上。 沟槽设置在翅片形结构之间。 间隔层设置在沟槽的侧壁上，其中间隔层具有比翅片形结构的顶表面低的顶表面。 虚拟栅极结构设置在鳍状结构上并横跨沟槽。

公开(公告)号：US20170025512A1

公开(公告)日：2017-01-26

申请号：US15283445

申请日：2016-10-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/42376 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/4232 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66545

Abstract: A semiconductor device having metal gate includes a substrate, a metal gate formed on the substrate, a pair of spacers formed on sidewalls of the metal gate, a contact etch stop layer (CESL) covering the spacers, an insulating cap layer formed on the metal gate, the spacers and the CESL, and an ILD layer surrounding the metal gate, the spacers, the CESL and the insulating cap layer. The metal gate, the spacers and the CESL include a first width, and the insulating cap layer includes a second width. The second width is larger than the first width. And a bottom of the insulating cap layer concurrently contacts the metal gate, the spacers, the CESL, and the ILD layer.

Abstract translation: 具有金属栅极的半导体器件包括衬底，形成在衬底上的金属栅极，形成在金属栅极的侧壁上的一对间隔物，覆盖间隔物的接触蚀刻停止层（CESL），形成在金属栅极上的绝缘盖层 栅极，间隔物和CESL，以及围绕金属栅极，间隔物，CESL和绝缘帽层的ILD层。 金属栅极，间隔物和CESL包括第一宽度，绝缘帽层包括第二宽度。 第二宽度大于第一宽度。 并且绝缘盖层的底部同时与金属栅极，间隔物，CESL和ILD层接触。

公开(公告)号：US20160334208A1

公开(公告)日：2016-11-17

申请号：US14737475

申请日：2015-06-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Yi-Jing Wang

IPC: G01B11/26

CPC classification number: G03F7/70633

Abstract: The present invention provides an overlay mark information, including at least a pair of first overlay mark patterns disposed in a first layer, each first overlay mark pattern consisting of a plurality of first mark units arranged along a first direction, where each first mark unit includes at least one first pattern and at least one second pattern, and the dimension of the first pattern is different from the dimension of the second pattern. The overlay mark information also includes at least a pair of second overlay patterns disposed in the first layer, each second overlay mark pattern consisting of a plurality of second mark units arranged along the first direction, where the pattern of each first mark unit is the same as the pattern of each second mark unit after 180 degrees rotated.

Abstract translation: 本发明提供一种重叠标记信息，其包括设置在第一层中的至少一对第一覆盖标记图案，每个第一覆盖标记图案由沿着第一方向布置的多个第一标记单元组成，其中每个第一标记单元包括 至少一个第一图案和至少一个第二图案，并且所述第一图案的尺寸不同于所述第二图案的尺寸。 覆盖标记信息还包括设置在第一层中的至少一对第二覆盖图案，每个第二覆盖标记图案由沿着第一方向布置的多个第二标记单元组成，其中每个第一标记单元的图案是相同的 作为180度旋转后的每个第二标记单元的图案。

公开(公告)号：US09496176B1

公开(公告)日：2016-11-15

申请号：US15176142

申请日：2016-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung ,  En-Chiuan Liou

IPC: H01L21/768 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76831 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/485 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: A semiconductor device includes a semiconductor structure, a plurality of gate structures, at least one source/drain structure, at least one trench, a dielectric pattern, and a conductive structure. The gate structures are disposed on the semiconductor structure. The source/drain structure is disposed between two adjacent gate structures. The trench is disposed between the two adjacent gate structures and corresponding to the source/drain structure. The dielectric pattern is disposed on sidewalls of the trench. The conductive structure is disposed in the trench and electrically connected to the source/drain structure. The conductive structure includes a first portion surrounded by the dielectric pattern and a second portion connected to the source/drain structure, and the first portion is disposed on the second portion. A width of the first portion is smaller than a width of the second portion.

Abstract translation: 半导体器件包括半导体结构，多个栅极结构，至少一个源极/漏极结构，至少一个沟槽，电介质图案和导电结构。 栅极结构设置在半导体结构上。 源极/漏极结构设置在两个相邻栅极结构之间。 沟槽设置在两个相邻栅极结构之间并对应于源极/漏极结构。 电介质图案设置在沟槽的侧壁上。 导电结构设置在沟槽中并电连接到源极/漏极结构。 导电结构包括被电介质图案包围的第一部分和连接到源极/漏极结构的第二部分，第一部分设置在第二部分上。 第一部分的宽度小于第二部分的宽度。