公开(公告)号：US09059202B2

公开(公告)日：2015-06-16

申请号：US13807315

申请日：2011-11-30

Applicant: Yan Jin

Inventor： Yan Jin

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/66477 ,  H01L29/42368 ,  H01L29/78 ,  H01L29/7836

Abstract: A Metal-Oxide-Semiconductor (MOS) device is disclosed. The MOS device includes a substrate, a well region formed in the substrate, and a gate located on the substrate. The MOS device also includes a first lightly-doped region arranged in the well region at a first side of the gate and overlapping with the gate, and a second lightly-doped region arranged in the well region at a second side of the gate and overlapping with the gate. Further, the MOS device includes a first heavily-doped region formed in the first lightly-doped region, and a second heavily-doped region formed in the second lightly-doped region. The MOS device also includes a first high-low-voltage gate oxide boundary arranged between the first heavily-doped region and the gate, and a second high-low-voltage gate oxide boundary arranged between the second heavily-doped region and the gate. The gate covers the first high-low-voltage gate oxide boundary and the second high-low-voltage gate oxide boundary at the first side and the second side of the gate, respectively.

Abstract translation: 公开了一种金属氧化物半导体（MOS）器件。 MOS器件包括衬底，形成在衬底中的阱区和位于衬底上的栅极。 MOS器件还包括布置在栅极的第一侧的阱区中并与栅极重叠的第一轻掺杂区域和布置在栅极第二侧的阱区中的第二轻掺杂区域，并且重叠 与门。 此外，MOS器件包括形成在第一轻掺杂区域中的第一重掺杂区域和形成在第二轻掺杂区域中的第二重掺杂区域。 MOS器件还包括布置在第一重掺杂区域和栅极之间的第一高低电压栅极氧化物边界和布置在第二重掺杂区域和栅极之间的第二高低压栅极氧化物边界。 栅极分别在栅极的第一侧和第二侧覆盖第一高低压栅极氧化物边界和第二高低压栅极氧化物边界。

公开(公告)号：US09040410B2

公开(公告)日：2015-05-26

申请号：US14130482

申请日：2013-05-10

Applicant: CSMC Technologies Fab2 Co., Ltd.

Inventor： Xin Yang

IPC: H01L23/544 ,  G03F7/20 ,  G03F9/00 ,  H01L21/00

CPC classification number: H01L23/544 ,  G03F7/20 ,  G03F9/708 ,  H01L21/00 ,  H01L2223/54433 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fabrication method for semiconductor devices is provided. The method comprises: depositing a dielectric layer that includes a plurality of functional layers, and forming a contact hole, or through hole, and a metal layer. The forming of the contact hole, or through hole, and the metal layer comprises performing photolithography on regions corresponding to a marking label for the photolithography of the dielectric layer and the metal layer. On at least one of the functional layers, the performing photolithography on regions corresponding to a marking label for the photolithography comprises limiting the photolithography to the metal layer thereof. A semiconductor device thus fabricated is also provided. The method and device do not affect the reading of the marking label, and also can avoid the problem of defocusing in the vicinity of the marking label.

Abstract translation: 提供了半导体器件的制造方法。 该方法包括：沉积包括多个功能层的介电层，以及形成接触孔或通孔以及金属层。 接触孔或通孔以及金属层的形成包括在对应于用于电介质层和金属层的光刻的标记标签的区域上进行光刻。 在至少一个功能层上，对应于用于光刻的标记标签的区域上的执行光刻包括将光刻限制到其金属层。 还提供了如此制造的半导体器件。 该方法和装置不影响标记标签的读数，也可以避免标记标签附近散焦的问题。

公开(公告)号：US08889535B2

公开(公告)日：2014-11-18

申请号：US13807305

申请日：2011-09-01

Applicant: Hua Song ,  Hsiao-Chia Wu ,  Tse-Huang Lo

Inventor： Hua Song ,  Hsiao-Chia Wu ,  Tse-Huang Lo

IPC: H01L21/425 ,  H01L21/265 ,  H01L21/74 ,  H01L29/02 ,  H01L29/08

CPC classification number: H01L21/265 ,  H01L21/26513 ,  H01L21/74 ,  H01L29/02 ,  H01L29/0821

Abstract: The present disclosure provides a semiconductor device and a method for fabricating a semiconductor buried layer. The method includes: preparing a substrate which includes a first oxide layer; forming a first buried layer region in the surface of the substrate by using a photoresist layer with a first buried layer region pattern as a mask, in which a doping state of the first buried layer region is different from a doping state of other region of the substrate; forming a second oxide layer on the surface of the substrate and the first buried layer region; and forming a second buried layer region in the surface of the substrate through self alignment process by using the second oxide layer as a mask. The method disclosed by the present disclosure reduces the complexity of the buried layer procedures and the cost thereof, as well as the probability of crystal defects.

Abstract translation: 本公开提供了半导体器件和制造半导体掩埋层的方法。 该方法包括：制备包括第一氧化物层的衬底; 通过使用具有第一掩埋层区域图案的光致抗蚀剂层作为掩模，在所述基板的表面中形成第一掩埋层区域，其中所述第一掩埋层区域的掺杂状态与所述第一掩埋层区域的其他区域的掺杂状态不同 基质; 在所述基板的表面和所述第一掩埋层区域上形成第二氧化物层; 以及通过使用第二氧化物层作为掩模通过自对准工艺在衬底的表面中形成第二掩埋层区域。 本发明公开的方法降低了掩埋层工艺的复杂性及其成本，以及晶体缺陷的可能性。

公开(公告)号：US08836427B2

公开(公告)日：2014-09-16

申请号：US13807304

申请日：2011-11-18

Applicant: Liang Cheng

Inventor： Liang Cheng

IPC: H03F3/45 ,  H03F3/30

CPC classification number: H03F3/45192 ,  H03F3/3016 ,  H03F3/3028 ,  H03F3/45076 ,  H03F3/45183 ,  H03F2200/456 ,  H03F2203/45248 ,  H03F2203/45264 ,  H03F2203/45308 ,  H03F2203/45352 ,  H03F2203/45526 ,  H03F2203/45674 ,  H03F2203/45692

Abstract: A folded cascode operational amplifier is disclosed. The folded cascode operational amplifier includes a first current source, a second current source, and a first voltage terminal connected to the first current source and the second current source. The folded cascode operational amplifier also includes a first input-transistor connected to the first current source in series, and a second input-transistor connected to the second current source in series. Further, the folded cascode operational amplifier includes a tail current source connected to a connection point between the first input-transistor and the second input-transistor, a load current source, and a second voltage terminal connected to the tail current source and the load current source. The folded cascode operational amplifier also includes an output-transistor connected to the load current source, and an output-terminal arranged between the second current source and the second input-transistor and connected to the output-transistor. The second current source is a mirroring current source of the first current source, and a ratio of a current passing through the second current source to a current passing through the first current source is greater than one.

Abstract translation: 公开了折叠共源共栅运算放大器。 折叠共源共栅运算放大器包括第一电流源，第二电流源和连接到第一电流源和第二电流源的第一电压端。 折叠共源共栅运算放大器还包括串联连接到第一电流源的第一输入晶体管和串联连接到第二电流源的第二输入晶体管。 此外，折叠共源共栅运算放大器包括连接到第一输入晶体管和第二输入晶体管之间的连接点的尾电流源，负载电流源和连接到尾电流源和负载电流的第二电压端 资源。 折叠的共源共栅运算放大器还包括连接到负载电流源的输出晶体管和布置在第二电流源和第二输入晶体管之间并连接到输出晶体管的输出端。 第二电流源是第一电流源的镜像电流源，并且通过第二电流源的电流与通过第一电流源的电流的比值大于1。

公开(公告)号：US20140167045A1

公开(公告)日：2014-06-19

申请号：US14236473

申请日：2012-06-07

Applicant: Zheng Bian

Inventor： Zheng Bian

IPC: H01L21/66 ,  H01L21/306

CPC classification number: H01L21/30604 ,  H01L22/12 ,  H01L22/30

Abstract: A test pattern for testing a trench POLY over-etched step is provided. The test pattern is a trench (14) formed on a substrate (1); the trench (14) comprises a bottom surface and two side surfaces extending from the bottom surface; the trench (14) is formed on the substrate (1) with a preset angle of non-90° formed between the longitudinal direction (L) thereof and the longitudinal direction (X) of a wafer scribing trench. The test pattern can extend the scanning length of a step scanning equipment without changing the width of the trench.

Abstract translation: 提供了用于测试沟槽POLY过蚀刻步骤的测试图案。 测试图案是形成在基板（1）上的沟槽（14）。 沟槽（14）包括底表面和从底表面延伸的两个侧表面; 在基板（1）上形成有在其长度方向（L）与晶片划片槽的长度方向（X）之间形成的非90°的预设角度的沟槽（14）。 测试图案可以延长步进扫描设备的扫描长度，而不改变沟槽的宽度。

公开(公告)号：US20140154878A1

公开(公告)日：2014-06-05

申请号：US14130460

申请日：2012-07-31

Applicant: Yawei Chen ,  Zhihon Jian

Inventor： Yawei Chen ,  Zhihon Jian

IPC: H01L21/306

CPC classification number: H01L21/306 ,  H01L21/0206 ,  H01L21/02071 ,  H01L21/28123 ,  H01L21/28273 ,  H01L21/32139 ,  H01L27/11521

Abstract: An embodiment of a NOR Flash device manufacturing method is disclosed, which includes: providing a substrate having a first polycrystalline silicon layer disposed thereon; forming a first hard mask layer on the first polycrystalline silicon layer; etching the first hard mask layer to form a first opening, and cleaning a gas pipeline connected to an etching cavity before etching the first hard mask layer; forming a second hard mask layer on the first hard mask layer, and the second hard mask layer covers the bottom and side wall of the first opening; etching the second hard mask layer to form a second opening, the width of the second opening is smaller than the width of the first opening; etching the first polycrystalline silicon, forming a floating gate. The NOR Flash device manufacturing method of the present invention improves the yield of the NOR Flash device.

Abstract translation: 公开了一种NOR闪存器件制造方法的实施例，其包括：提供其上设置有第一多晶硅层的衬底; 在所述第一多晶硅层上形成第一硬掩模层; 蚀刻第一硬掩模层以形成第一开口，以及在蚀刻第一硬掩模层之前清洁连接到蚀刻腔的气体管线; 在第一硬掩模层上形成第二硬掩模层，第二硬掩模层覆盖第一开口的底壁和侧壁; 蚀刻第二硬掩模层以形成第二开口，第二开口的宽度小于第一开口的宽度; 蚀刻第一多晶硅，形成浮栅。 本发明的NOR闪存器件制造方法提高了NOR闪存器件的产量。

公开(公告)号：US20130113052A1

公开(公告)日：2013-05-09

申请号：US13807308

申请日：2011-11-18

Applicant: Le Wang

Inventor： Le Wang

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L29/1033 ,  H01L29/66477 ,  H01L29/66651

Abstract: A Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is disclosed. The MOSFET includes a substrate, a well region formed in the substrate, a shallow channel layer, a channel, a gate oxide layer, a gate region, a source region, and a drain region. The shallow channel layer is formed on a portion of the well region and includes a first shallow channel region and a second shallow channel region. The channel is arranged between the first shallow channel region and the second shallow channel region and connects the first shallow channel region and the second shallow channel region. Further, the gate oxide layer is formed on a portion of the well region between the first shallow channel region and the second shallow channel region and includes a first gate oxide region and a second gate oxide region arranged on different sides of the channel. The gate region is formed on the channel and the gate oxide layer; the source region is formed in the first shallow channel region and vertically extends into the well region under the first shallow channel region; and the drain region is formed in the second shallow channel region and vertically extends into the well region under the second shallow channel region.

Abstract translation: 公开了一种金属氧化物半导体场效应晶体管（MOSFET）。 MOSFET包括衬底，形成在衬底中的阱区，浅沟道层，沟道，栅极氧化物层，栅极区，源极区和漏极区。 浅沟道层形成在阱区的一部分上，并且包括第一浅沟道区和第二浅沟道区。 通道布置在第一浅沟道区域和第二浅沟道区域之间，并且连接第一浅沟道区域和第二浅沟道区域。 此外，栅极氧化层形成在第一浅沟道区域和第二浅沟道区域之间的阱区域的一部分上，并且包括布置在沟道的不同侧上的第​​一栅极氧化物区域和第二栅极氧化物区域。 栅极区形成在沟道和栅极氧化物层上; 源极区域形成在第一浅沟道区域中并垂直延伸到第一浅沟道区域下方的阱区域中; 并且所述漏极区域形成在所述第二浅沟道区域中并且垂直延伸到所述第二浅沟道区域下方的阱区域中。

公开(公告)号：US20130037878A1

公开(公告)日：2013-02-14

申请号：US13695013

申请日：2011-06-23

Applicant: Le Wang

Inventor： Le Wang

IPC: H01L29/78 ,  H01L21/20

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395

Abstract: A method for fabricating VDMOS devices includes providing a semiconductor substrate; forming a first N-type epitaxial layer on the semiconductor substrate; forming a hard mask layer with an opening on the first N-type epitaxial layer; etching the first N-type epitaxial layer along the opening until the semiconductor substrate is exposed, to form P-type barrier figures; forming a P-type barrier layer in the P-type barrier figures, the P-type barrier layer having a same thickness as that of the first N-type epitaxial layer; removing the hard mask layer; forming a second N-type epitaxial layer on the first N-type epitaxial layer and the P-type barrier layer; forming a gate on the second N-type epitaxial layer; forming a source in the second N-type epitaxial layer on both side of the gate; and forming a drain on the back of the semiconductor substrate relative to the gate and the source.

Abstract translation: 一种用于制造VDMOS器件的方法包括：提供半导体衬底; 在所述半导体衬底上形成第一N型外延层; 在第一N型外延层上形成具有开口的硬掩模层; 沿着开口蚀刻第一N型外延层直到半导体衬底露出，以形成P型势垒图; 在P型势垒图中形成P型势垒层，P型势垒层的厚度与第一N型外延层的厚度相同; 去除硬掩模层; 在第一N型外延层和P型势垒层上形成第二N型外延层; 在第二N型外延层上形成栅极; 在栅极两侧的第二N型外延层中形成源极; 以及在所述半导体衬底的背面上相对于所述栅极和所述源形成漏极。

公开(公告)号：US20130001747A1

公开(公告)日：2013-01-03

申请号：US13519252

申请日：2010-12-02

Applicant: Le Wang ,  Linchun Gui ,  Kongwei Zhu ,  Zhiyong Zhao

Inventor： Le Wang ,  Linchun Gui ,  Kongwei Zhu ,  Zhiyong Zhao

IPC: H01L21/331 ,  H01L29/732

CPC classification number: H01L29/66272

Abstract: A method for manufacturing a bipolar transistor includes forming a first epitaxial layer on a semiconductor substrate, forming a second epitaxial layer on the first epitaxial layer, forming an oxide layer on the second epitaxial layer, etching the oxide layer to form an opening in which the second epitaxial layer is exposed, and forming a third epitaxial layer in the opening. The first and third epitaxial layers have a first-type conductivity, and the second epitaxial layer has a second-type conductivity.

Abstract translation: 一种用于制造双极晶体管的方法，包括在半导体衬底上形成第一外延层，在第一外延层上形成第二外延层，在第二外延层上形成氧化层，蚀刻氧化物层以形成开口， 暴露第二外延层，并在开口中形成第三外延层。 第一和第三外延层具有第一类型的导电性，第二外延层具有第二类型的导电性。

公开(公告)号：US12119395B2

公开(公告)日：2024-10-15

申请号：US17762212

申请日：2020-08-26

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Long Zhang ,  Jie Ma ,  Yan Gu ,  Sen Zhang ,  Jing Zhu ,  Jinli Gong ,  Weifeng Sun ,  Longxing Shi

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7394 ,  H01L29/0623 ,  H01L29/0834 ,  H01L29/1095

Abstract: An insulated gate bipolar transistor, comprising an anode second conductivity-type region and an anode first conductivity-type region provided on a drift region; the anode first conductivity-type region comprises a first region and a second region, and the anode second conductivity-type region comprises a third region and a fourth region, the dopant concentration of the first region being less than that of the second region, the dopant concentration of the third region being less than that of the fourth region, the third region being provided between the fourth region and a body region, the first region being provided below the fourth region, and the second region being provided below the third region and located between the first region and the body region.