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    IMAGING DEVICE AND IMAGING SYSTEM
    111.
    发明申请
    IMAGING DEVICE AND IMAGING SYSTEM 审中-公开

    公开(公告)号：US20180103182A1

    公开(公告)日：2018-04-12

    申请号：US15709816

    申请日：2017-09-20

    Applicant: CANON KABUSHIKI KAISHA

    Inventor： Maasa Ito ,  Tomoya Onishi

    IPC: H04N3/14 ,  H04N5/3745 ,  H04N5/345

    CPC classification number: H04N3/155 ,  H04N5/341 ,  H04N5/345 ,  H04N5/37457 ,  H04N5/376 ,  H04N5/772

    Abstract: An imaging device includes a plurality of pixels arranged in a plurality of rows, in which each of the plurality of pixels outputs a pixel signal; a row scanning unit that scans the plurality of pixels on a row basis; and an output unit that outputs first time information corresponding to a processing timing of the pixel signal on one of the plurality of rows and second time information corresponding to the pixel signal on another of the plurality of rows and having a different value from the first time information.

    Imaging device
    113.
    发明授权
    Imaging device 有权

    公开(公告)号：US09894297B2

    公开(公告)日：2018-02-13

    申请号：US15406824

    申请日：2017-01-16

    Applicant: Panasonic Intellectual Property Management Co., Ltd.

    Inventor： Hidenari Kanehara ,  Masashi Murakami ,  Takayoshi Yamada ,  Kazuko Nishimura ,  Yasuo Miyake

    IPC: H04N5/355 ,  H04N5/369 ,  H04N5/3745 ,  H04N5/376

    CPC classification number: H04N5/35563 ,  H04N5/3559 ,  H04N5/3696 ,  H04N5/374 ,  H04N5/37452 ,  H04N5/376

    Abstract: An imaging device includes a pixel cell including: a first photoelectric converter that generates a first electrical signal; and a first signal detection circuit that detects the first electrical signal. The first signal detection circuit includes: a first transistor one of a source and a drain of which is electrically connected to the first photoelectric converter; a first capacitor having first and second ends, the first end being electrically connected to the other of the source and the drain of the first transistor, a reference voltage being applied to the second end; and a second transistor having a gate electrically connected to the first photoelectric converter. The pixel cell outputs, in one frame period, a first image signal and a second image signal in sequence, the first image signal being output when the first transistor is off, the second image signal being output when the first transistor is on.

    CONTROL DEVICE, CONTROL METHOD, AND SOLID-STATE IMAGING DEVICE
    115.
    发明申请
    CONTROL DEVICE, CONTROL METHOD, AND SOLID-STATE IMAGING DEVICE 审中-公开

    公开(公告)号：US20170257589A1

    公开(公告)日：2017-09-07

    申请号：US15503106

    申请日：2015-08-14

    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION

    Inventor： Tomoyasu TATE

    IPC: H04N5/376 ,  H04N5/353

    CPC classification number: H04N5/376 ,  H04N5/353 ,  H04N5/374 ,  H04N5/378

    Abstract: The present disclosure relates to a control device, a control method, and a solid-state imaging device that enable a larger number of shutter row addresses to be set at the same time. A vertical selection decoder and a latch circuit set shutter row addresses that identify rows of pixels for which an electronic shutter operation is performed, of pixels arranged in a matrix manner, on the basis of a start address and an end address of the shutter row addresses. The present disclosure is applicable to, for example, a CMOS image sensor that sets the shutter row addresses.

    Imaging apparatus, method of driving the same, and imaging system
    116.
    发明授权
    Imaging apparatus, method of driving the same, and imaging system 有权

    公开(公告)号：US09749570B2

    公开(公告)日：2017-08-29

    申请号：US14745574

    申请日：2015-06-22

    Applicant: CANON KABUSHIKI KAISHA

    Inventor： Takanori Yamashita ,  Yoshikazu Yamazaki

    IPC: H04N5/378 ,  H04N5/376 ,  H04N5/357

    CPC classification number: H04N5/378 ,  H04N5/357 ,  H04N5/376

    Abstract: Provided is an imaging apparatus, including: a driving circuit switching between a current supplying state and a current non-supplying state of the current sources included in column circuits in the respective columns; at least one second readout line to which image signals output from the column circuits in the respective columns are input; switches each having one terminal and another terminal; and a switch control circuit configured to output switch control signals for respectively controlling the switches to be turned on or off, each of the one terminals being connected to corresponding second readout line and each of the another terminals being connected commonly to an output line, in which, in a period in which the switch control signals for respectively controlling the switches to be turned on are output, the number of the current sources controlled to be in the current supplying state by the driving circuit is constant.

    MATRIX TYPE INTEGRATED CIRCUIT WITH FAULT ISOLATION CAPABILITY
    117.
    发明申请
    MATRIX TYPE INTEGRATED CIRCUIT WITH FAULT ISOLATION CAPABILITY 有权

    公开(公告)号：US20170213867A1

    公开(公告)日：2017-07-27

    申请号：US15007312

    申请日：2016-01-27

    Applicant: VAREX IMAGING CORPORATION

    Inventor： Pieter Gerhard Roos

    IPC: H01L27/146 ,  G01R31/26

    CPC classification number: H01L27/14658 ,  G01R31/2601 ,  H01L27/14625 ,  H01L27/14634 ,  H01L27/14636 ,  H04N5/32 ,  H04N5/367 ,  H04N5/376

    Abstract: Technology is described for selectively disconnecting a communal module (e.g., horizontal power and signal distribution network) from conductive traces (e.g., vertical columns) that are coupled to cell elements. In one example, a matrix type integrated circuit includes a two dimensional (2D) array of cell elements, a plurality of conductive traces, a communal module, and a plurality of switches. Each cell element in the 2D array provides a similar function. The plurality of conductive traces is substantially parallel to a first axis of the 2D array. Each conductive trace is coupled to a conductive interconnect of cell elements adjacent to the conductive trace. The communal module is configured to provide distribution of at least one electrical signal to the cell elements in the 2D array via at least two conductive traces that are substantially parallel to the first axis.

    IMAGE SENSOR CONFIGURATION
    118.
    发明申请
    IMAGE SENSOR CONFIGURATION 有权

    公开(公告)号：US20170187936A1

    公开(公告)日：2017-06-29

    申请号：US15151240

    申请日：2016-05-10

    Applicant: STMicroelectronics (Research & Development) Limite

    Inventor： Jeffrey M. Raynor

    IPC: H04N5/235 ,  H01L27/146 ,  H04N9/04

    CPC classification number: H04N5/235 ,  H01L27/14609 ,  H01L27/14643 ,  H04N5/2353 ,  H04N5/37452 ,  H04N5/376 ,  H04N9/045

    Abstract: An image sensor has an array of light-sensitive pixels. Each pixel of the array includes a photodiode and a plurality of capacitors configured to store charge from the photodiode. The image sensor has an address decoder, coupled to the array of light-sensitive pixels. In at least one mode of operation, portions of the array of light-sensitive pixels to capture respective image exposures. The portions may include interlaced rows of pixels of the array of light-sensitive pixels, blocks of rows of pixels of the array of light-sensitive pixels, interlaced columns of pixels of the array of light-sensitive pixels, interlaced columns and rows of pixels of the array of light-sensitive pixels, blocks of columns and rows of pixels of the array of light-sensitive pixels, etc.

    IMAGE SENSOR AND ELECTRONIC APPARATUS
    119.
    发明申请
    IMAGE SENSOR AND ELECTRONIC APPARATUS 有权

    公开(公告)号：US20170155865A1

    公开(公告)日：2017-06-01

    申请号：US15127510

    申请日：2015-04-03

    Applicant: SONY CORPORATION

    Inventor： Tsutomu NAKAJIMA ,  Atsushi MUTO

    IPC: H04N5/3745 ,  H04N5/376 ,  H01L27/146

    CPC classification number: H04N5/37455 ,  H01L27/14607 ,  H01L27/14634 ,  H01L27/14643 ,  H04N5/374 ,  H04N5/376

    Abstract: The present technology relates to an image sensor and an electronic apparatus which can make the image sensor a smaller without degrading performance of the image sensor. The image sensor includes a pixel array unit in which pixels including photoelectric conversion elements are arranged in a two dimensional manner, a row circuit configured to control row scanning of the pixel array unit, and a column processing unit configured to convert an analog signal read out from the pixel array unit into a digital signal. The pixel array unit is disposed on a first-layer substrate, and the row circuit and the column processing unit are disposed on different substrates which are underlying layers of the first-layer substrate and which are laminated on the first-layer substrate. The present technology is applicable to the image sensor.

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