公开(公告)号：US20240143445A1

公开(公告)日：2024-05-02

申请号：US17974981

申请日：2022-10-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Alicia Wen Ju Yurie Leong ,  William Robert Alverson ,  Joshua Taylor Knight ,  Jerry Anton Ahrens ,  Grant Evan Ley ,  Anil Harwani ,  Amitabh Mehra ,  Jayesh Hari Joshi

IPC: G06F11/14 ,  G11C29/52

CPC classification number: G06F11/1417 ,  G11C29/52

Abstract: Stability testing for memory overclocking is described. In accordance with the described techniques, operation of a memory with overclocked memory settings is testing during a boot up process of a computing device. Test results based on the testing are exposed via a user interface. The test results predict a stability of the memory over a subsequent time period if the memory is configured to operate with the overclocked memory settings.

公开(公告)号：US20240143056A1

公开(公告)日：2024-05-02

申请号：US18218463

申请日：2023-07-05

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ILC

Inventor： Greg SADOWSKI ,  Sriram Sundarm ,  Stephen Kushnir ,  William C. Brantley ,  Michael J. Schulte

IPC: G06F1/28 ,  G05F1/625

CPC classification number: G06F1/28 ,  G05F1/625

Abstract: A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.

公开(公告)号：US11972271B2

公开(公告)日：2024-04-30

申请号：US17565593

申请日：2021-12-30

Applicant: Advanced Micro Devices, Inc.

Inventor： William Herz

IPC: G06F1/3206 ,  G06F9/445

CPC classification number: G06F9/4451 ,  G06F1/3206

Abstract: A processing device is provided which comprises memory and a processor, in communication with the memory. The processor is configured to acquire information indicating a sensory perception of a user, determine settings for one or more parameters used to control operation of the device based on the information indicating the sensory perception of the user and control the operation of the device by tuning the one or more parameters according to the determined settings.

公开(公告)号：US20240135626A1

公开(公告)日：2024-04-25

申请号：US18402315

申请日：2024-01-02

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Michael Mantor ,  Laurent Lefebvre ,  Mark Fowler ,  Timothy Kelley ,  Mikko Alho ,  Mika Tuomi ,  Kiia Kallio ,  Patrick Klas Rudolf Buss ,  Jari Antero Komppa ,  Kaj Tuomi

IPC: G06T15/00

CPC classification number: G06T15/005

Abstract: A method, computer system, and a non-transitory computer-readable storage medium for performing primitive batch binning are disclosed. The method, computer system, and non-transitory computer-readable storage medium include techniques for generating a primitive batch from a plurality of primitives, computing respective bin intercepts for each of the plurality of primitives in the primitive batch, and shading the primitive batch by iteratively processing each of the respective bin intercepts computed until all of the respective bin intercepts are processed.

公开(公告)号：US11966339B1

公开(公告)日：2024-04-23

申请号：US17957205

申请日：2022-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander Joseph Branover

IPC: G06F12/0868 ,  G06F12/084

CPC classification number: G06F12/0868 ,  G06F12/084 ,  G06F2212/1032

Abstract: Selecting between basic and global persistent flush modes is described. In accordance with the described techniques, a system includes a data fabric in electronic communication with at least one cache and a controller configured to select between operating in a global persistent flush mode and a basic persistent flush mode based on an available flushing latency of the system, control the at least one cache to flush dirty data to the data fabric in response to a flush event trigger while operating in the global persistent flush mode, and transmit a signal to switch control to an application to flush the dirty data from the at least one cache to the data fabric while operating in the basic persistent flush mode.

公开(公告)号：US11966328B2

公开(公告)日：2024-04-23

申请号：US17126977

申请日：2020-12-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Onur Kayiran ,  Mohamed Assem Ibrahim ,  Shaizeen Aga

IPC: G06F12/06

CPC classification number: G06F12/06 ,  G06F2212/1041

Abstract: A memory module includes register selection logic to select alternate local source and/or destination registers to process PIM commands. The register selection logic uses an address-based register selection approach to select an alternate local source and/or destination register based upon address data specified by a PIM command and a split address maintained by a memory module. The register selection logic may alternatively use a register data-based approach to select an alternate local source and/or destination register based upon data stored in one or more local registers. A PIM-enabled memory module configured with the register selection logic described herein is capable of selecting an alternate local source and/or destination register to process PIM commands at or near the PIM execution unit where the PIM commands are executed.

公开(公告)号：US20240128192A1

公开(公告)日：2024-04-18

申请号：US18047482

申请日：2022-10-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Suphachai Sutanthavibul ,  Richard T. Schultz

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/48 ,  H01L23/525

CPC classification number: H01L23/5286 ,  H01L21/76895 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/525

Abstract: An apparatus and method for efficiently routing power signals across a semiconductor die. In various implementations, an integrated circuit includes a micro through silicon via (TSV) that traverses a silicon substrate layer to a backside metal layer. The integrated circuit also includes power switches. The integrated circuit routes a power supply signal from the output of a power switch to a frontside power rail using the micro TSV and the backside metal layer. The integrated circuit also routes the power supply signal from the output of the power switch to the frontside power rail using a frontside metal layer. Therefore, the frontside metal layer and the backside metal layer provide power connection redundancy that increases charge sharing, improves wafer yield, reduces voltage droop, and reduces on-die area. In addition, the process routes a ground reference voltage level using both a frontside power rail and a backside power rail.

公开(公告)号：US11960435B2

公开(公告)日：2024-04-16

申请号：US17692147

申请日：2022-03-10

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Pradeep Jayaraman ,  Dean Gonzales ,  Gerald R. Talbot ,  Ramon A. Mangaser ,  Michael J. Tresidder ,  Prasant Kumar Vallur ,  Srikanth Reddy Gruddanti ,  Krishna Reddy Mudimela Venkata ,  David H. McIntyre

IPC: G06F13/42 ,  H01L25/065

CPC classification number: G06F13/4291 ,  G06F13/4286 ,  H01L25/0652

Abstract: A semiconductor package for skew matching in a die-to-die interface, including: a first die; a second die aligned with the first die such that each connection point of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die; and a plurality of connection paths of a substantially same length, wherein each connection path of the plurality of connection paths couples a respective connection point of the first plurality of connection points to the corresponding connection point of the second plurality of connection points.

公开(公告)号：US20240119993A1

公开(公告)日：2024-04-11

申请号：US18390431

申请日：2023-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Aaron John Nygren ,  Kathik Gopalakrishnan ,  Tsun Ho Liu

IPC: G11C11/4076 ,  G06F1/08 ,  G06F1/10 ,  G06F3/06

CPC classification number: G11C11/4076 ,  G06F1/08 ,  G06F1/10 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0671

Abstract: A memory controller monitors memory command selected for dispatch to the memory and sends commands controlling a read clock state. A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously, and as a strobe signal that is active only in response to the memory receiving a read command.

公开(公告)号：US20240119010A1

公开(公告)日：2024-04-11

申请号：US18380954

申请日：2023-10-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Steven RAASCH ,  Andrew G. KEGEL

IPC: G06F12/1009 ,  G06F9/50 ,  G06F11/07 ,  G06F12/02 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1027 ,  G06F12/123

CPC classification number: G06F12/1009 ,  G06F9/5016 ,  G06F11/0772 ,  G06F12/0246 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1027 ,  G06F12/123

Abstract: A processing system includes a primary processor and a co-processor. The primary processor is couplable to a memory subsystem having at least one memory and operating to execute system software employing memory address translations based on one or more page tables stored in the memory subsystem. The co-processor is likewise couplable to the memory subsystem and operates to perform iterations of a page table walk through one or more page tables maintained for the memory subsystem and to perform one or more page management operations on behalf of the system software based the iterations of the page table walk. The page management operations performed by the co-processor include analytic data aggregation, free list management and page allocation, page migration management, page table error detection, and the like.