公开(公告)号：US20140061589A1

公开(公告)日：2014-03-06

申请号：US14057204

申请日：2013-10-18

Applicant: Ravi Pillarisetty ,  Been-Yin Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

Inventor： Ravi Pillarisetty ,  Been-Yin Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

IPC: H01L29/775

CPC classification number: H01L27/092 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7782

Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

Abstract translation: 量子阱晶体管具有锗量子阱沟道区域。 含硅蚀刻停止层提供了靠近通道的栅电介质的容易放置。 III-V族阻挡层增加了通道的应变。 通道区域上方和下方的分级硅锗层提高性能。 多栅极电介质材料允许使用高k值栅极电介质。

公开(公告)号：US08575596B2

公开(公告)日：2013-11-05

申请号：US13647952

申请日：2012-10-09

Applicant: Ravi Pillarisetty ,  Jack T. Kavalieros ,  Willy Rachmady ,  Uday Shah ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Gilbert Dewey ,  Been Y. Jin ,  Robert S. Chau

Inventor： Ravi Pillarisetty ,  Jack T. Kavalieros ,  Willy Rachmady ,  Uday Shah ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Gilbert Dewey ,  Been Y. Jin ,  Robert S. Chau

IPC: H01L31/00

CPC classification number: H01L29/775 ,  B82Y10/00 ,  H01L21/76 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/66977 ,  H01L29/7782 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

Abstract translation: 公开了用于形成非平面锗量子阱结构的技术。 特别地，量子阱结构可以用IV或III-V族半导体材料实现，并且包括锗鳍结构。 在一个示例性情况下，提供了非平面量子阱器件，其包括具有衬底（例如硅上的SiGe或GaAs缓冲器），IV或III-V材料阻挡层（例如，SiGe或GaAs或 AlGaAs），掺杂层（例如，掺杂Δ/调制）和未掺杂的锗量子阱层。 在量子阱结构中形成未掺杂的锗鳍结构，以及沉积在鳍结构上的顶部势垒层。 栅极金属可以跨鳍片结构沉积。 排水/源极区域可以形成在翅片结构的相应端部处。

公开(公告)号：US20130277714A1

公开(公告)日：2013-10-24

申请号：US13977188

申请日：2011-12-09

Applicant: Van H. Le ,  Benjamin Chu-Kung ,  Harold Hal W. Kennel ,  Willy Rachmady ,  Ravi Pillarisetty ,  Jack T. Kavalieros

Inventor： Van H. Le ,  Benjamin Chu-Kung ,  Harold Hal W. Kennel ,  Willy Rachmady ,  Ravi Pillarisetty ,  Jack T. Kavalieros

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/283 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66477 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78681 ,  H01L29/78687 ,  H01L29/78696

Abstract: Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.

Abstract translation: 提供具有包括压缩和拉伸应变外延材料的交替层的沟道区的晶体管结构。 交替的外延层可以在单和多晶体管结构中形成沟道区。 在替代实施例中，两个交替层中的一个被选择性地蚀刻掉以形成剩余材料的纳米带或纳米线。 得到的应变纳米带或纳米线形成晶体管结构的沟道区。 还提供了包括晶体管的计算设备，晶体管包括由交替的压缩和拉伸应变外延层组成的沟道区，以及包括包含由应变纳米带或纳米线组成的沟道区的晶体管的计算器件。

公开(公告)号：US08501508B2

公开(公告)日：2013-08-06

申请号：US13479121

申请日：2012-05-23

Applicant: Prashant Majhi ,  Mantu Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

Inventor： Prashant Majhi ,  Mantu Hudait ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Titash Rakshit ,  Willman Tsai

IPC: H01L21/00

CPC classification number: H01L29/66431 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76897 ,  H01L29/152 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848 ,  H01L29/802

Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

Abstract translation: 所描述的实施例包括具有金属源/漏极的应变晶体管量子阱（QW）沟道区，以及保形再生长源/漏极，以在MOS沟道区中赋予单轴应变。 沟道层的去除部分可以填充具有不同于沟道材料的晶格间隔的结合材料，以在通道中引起单轴应变，以及在沟道层中引起的双轴应变 顶部阻挡层和量子阱的底部缓冲层。

公开(公告)号：US08193567B2

公开(公告)日：2012-06-05

申请号：US12333248

申请日：2008-12-11

Applicant: Jack T. Kavalieros ,  Justin K. Brask ,  Brian S. Doyle ,  Uday Shah ,  Suman Datta ,  Mark L. Doczy ,  Matthew V. Metz ,  Robert S. Chau

Inventor： Jack T. Kavalieros ,  Justin K. Brask ,  Brian S. Doyle ,  Uday Shah ,  Suman Datta ,  Mark L. Doczy ,  Matthew V. Metz ,  Robert S. Chau

IPC: H01L29/76

CPC classification number: H01L21/823828 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1037 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.

Abstract translation: 一种能够将平面和非平面晶体管集成到体半导体衬底上的工艺，其中所有晶体管的沟道可在连续的宽度范围内定义。

公开(公告)号：US08120065B2

公开(公告)日：2012-02-21

申请号：US12541763

申请日：2009-08-14

Applicant: Suman Datta ,  Justin K. Brask ,  Been-Yih Jin ,  Jack T. Kavalieros ,  Mantu K. Hudait

Inventor： Suman Datta ,  Justin K. Brask ,  Been-Yih Jin ,  Jack T. Kavalieros ,  Mantu K. Hudait

IPC: H01L21/02

CPC classification number: H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/517 ,  H01L29/66628 ,  H01L29/7848 ,  Y10S438/933 ,  Y10S438/938

Abstract: Enhancement mode transistors are described where a Group III-N compound is used in the source and drain regions to place tensile strain on the channel. The source and drain regions may be raised or embedded, and fabricated in conjunction with recessed or raised compression regions for p channel transistors.

Abstract translation: 描述了增强模式晶体管，其中在源极和漏极区域中使用III-N族化合物以在通道上施加拉伸应变。 源极和漏极区域可以被凸起或嵌入，并且与用于p沟道晶体管的凹陷或凸起的压缩区域一起制造。

公开(公告)号：US08120063B2

公开(公告)日：2012-02-21

申请号：US12345489

申请日：2008-12-29

Applicant: Mantu K. Hudait ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Jack T. Kavalieros

Inventor： Mantu K. Hudait ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Jack T. Kavalieros

IPC: H01L29/267

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/66795

Abstract: Modulation-doped multi-gate devices are generally described. In one example, an apparatus includes a semiconductor substrate having a surface, one or more buffer films coupled to the surface of the semiconductor substrate, a first barrier film coupled to the one or more buffer films, a multi-gate fin coupled to the first barrier film, the multi-gate fin comprising a source region, a drain region, and a channel region of a multi-gate device wherein the channel region is disposed between the source region and the drain region, a spacer film coupled to the multi-gate fin, and a doped film coupled to the spacer film.

Abstract translation: 通常描述调制掺杂多栅极器件。 在一个示例中，设备包括具有表面的半导体衬底，耦合到半导体衬底的表面的一个或多个缓冲膜，耦合到该一个或多个缓冲膜的第一阻挡膜，耦合到第一 所述多栅极鳍片包括源极区域，漏极区域和多栅极器件的沟道区域，其中所述沟道区域设置在所述源极区域和所述漏极区域之间，间隔膜耦合到所述多栅极器件， 栅极鳍片以及耦合到间隔膜的掺杂膜。

公开(公告)号：US20120018781A1

公开(公告)日：2012-01-26

申请号：US13248197

申请日：2011-09-29

Applicant: Mantu K. Hudait ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Jack T. Kavalieros

Inventor： Mantu K. Hudait ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Jack T. Kavalieros

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/66795

Abstract: Modulation-doped multi-gate devices are generally described. In one example, an apparatus includes a semiconductor substrate having a surface, one or more buffer films coupled to the surface of the semiconductor substrate, a first barrier film coupled to the one or more buffer films, a multi-gate fin coupled to the first barrier film, the multi-gate fin comprising a source region, a drain region, and a channel region of a multi-gate device wherein the channel region is disposed between the source region and the drain region, a spacer film coupled to the multi-gate fin, and a doped film coupled to the spacer film.

Abstract translation: 通常描述调制掺杂多栅极器件。 在一个示例中，设备包括具有表面的半导体衬底，耦合到半导体衬底的表面的一个或多个缓冲膜，耦合到该一个或多个缓冲膜的第一阻挡膜，耦合到第一 所述多栅极鳍片包括源极区域，漏极区域和多栅极器件的沟道区域，其中所述沟道区域设置在所述源极区域和所述漏极区域之间，间隔膜耦合到所述多栅极器件， 栅极鳍片以及耦合到间隔膜的掺杂膜。

公开(公告)号：US20110284965A1

公开(公告)日：2011-11-24

申请号：US13204987

申请日：2011-08-08

Applicant: Ravi Pillarisetty ,  Uday Shah ,  Brian S. Doyle ,  Jack T. Kavalieros

Inventor： Ravi Pillarisetty ,  Uday Shah ,  Brian S. Doyle ,  Jack T. Kavalieros

IPC: H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L29/785

Abstract: Reducing external resistance of a multi-gate device using spacer processing techniques is generally described. In one example, a method includes depositing a sacrificial gate electrode to one or more multi-gate fins, the one or more multi-gate fins comprising a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions, patterning the sacrificial gate electrode such that the sacrificial gate electrode material is coupled to the gate region and substantially no sacrificial gate electrode is coupled to the source and drain regions of the one or more multi-gate fins, forming a dielectric film coupled to the source and drain regions of the one or more multi-gate fins, removing the sacrificial gate electrode from the gate region of the one or more to multi-gate fins, depositing spacer gate dielectric to the gate region of the one or more multi-gate fins wherein substantially no spacer gate dielectric is deposited to the source and drain regions of the one or more multi-gate fins, the source and drain regions being protected by the dielectric film, and etching the spacer gate dielectric to completely remove the spacer gate dielectric from the gate region area to be coupled with a final gate electrode except a remaining pre-determined thickness of spacer gate dielectric to be coupled with the final gate electrode that remains coupled with the dielectric film.

Abstract translation: 通常描述使用间隔物处理技术降低多栅极器件的外部电阻。 在一个示例中，一种方法包括将牺牲栅电极沉积到一个或多个多栅极散热片上，一个或多个多栅极鳍片包括栅极区域，源极区域和漏极区域，栅极区域设置在 源极和漏极区域，图案化牺牲栅极电极，使得牺牲栅电极材料耦合到栅极区域，并且基本上没有牺牲栅极电极耦合到一个或多个多栅极鳍片的源极和漏极区域，形成电介质 将一个或多个多栅极翅片的源极和漏极区域耦合到所述一个或多个多栅极散热片的栅极区域;将所述牺牲栅极电极从所述一个或多个至多个栅极鳍片的栅极区域移除;将间隔栅极电介质沉积到所述一个或多个栅极栅极栅极区域; 更多的多栅极鳍片，其中基本上没有间隔栅极电介质沉积到一个或多个多栅极鳍片的源极和漏极区域，源极和漏极区域被电介质保护 膜和蚀刻间隔栅极电介质以从栅极区域区域完全去除间隔栅极电介质，以与最终栅极电极耦合，除了与保持耦合的最终栅电极耦合的间隔栅极电介质的剩余预定厚度之外 与电介质膜。

公开(公告)号：US08022487B2

公开(公告)日：2011-09-20

申请号：US12111714

申请日：2008-04-29

Applicant: Ravi Pillarisetty ,  Jack T. Kavalieros ,  Titash Rakshit ,  Gilbert Dewey ,  Willy Rachmady

Inventor： Ravi Pillarisetty ,  Jack T. Kavalieros ,  Titash Rakshit ,  Gilbert Dewey ,  Willy Rachmady

IPC: H01L21/00

CPC classification number: H01L29/66545 ,  H01L29/66795

Abstract: Techniques and structures for increasing body dopant uniformity in multi-gate transistor devices are generally described. In one example, an electronic device includes a semiconductor substrate, a multi-gate fin coupled with the semiconductor substrate, the multi-gate fin comprising a source region, a drain region, and a gate region wherein the gate region is disposed between the source region and the drain region, the gate region being body-doped after a sacrificial gate structure is removed from the multi-gate fin and before a subsequent gate structure is formed, a dielectric material coupled with the source region and the drain region of the multi-gate fin, and the subsequent gate structure coupled to the gate region of the multi-gate fin.

Abstract translation: 通常描述用于增加多栅极晶体管器件中的体掺杂物均匀性的技术和结构。 在一个示例中，电子设备包括半导体衬底，与半导体衬底耦合的多栅极鳍片，多栅极鳍片，包括源极区域，漏极区域和栅极区域，其中栅极区域设置在源极 区域和漏极区域，在从多栅极鳍去除牺牲栅极结构之后并且在形成后续栅极结构之后，栅极区域被体掺杂，与多层栅极的源极区域和漏极区域耦合的介电材料 并且随后的栅极结构耦合到多栅极鳍的栅极区域。