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公开(公告)号：US10663295B2
公开(公告)日：2020-05-26
申请号：US15994117
申请日：2018-05-31
Applicant: SOCIONEXT INC.
Inventor： Shunsaku Imaki , Yukiteru Murao , Tetsuro Noguchi , Kenichi Ishida , Masato Suzuki , Kazuyuki Ohhashi
Abstract: A distance measurement system includes a pair of cameras and is arranged on a roof of a mobile object or an upper edge portion of a door of the mobile object. One of the cameras is arranged at a first portion on an upper surface of the roof or on the upper edge portion of the door, includes an optical axis oriented upward from the upper surface, and has a field of view in all directions around the optical axis. The other camera is arranged at a second portion different from the first portion on the upper surface of the roof or the upper edge portion of the door, includes an optical axis oriented upward from the upper surface, and has a field of view in all directions around the optical axis. Distance measurement in all directions from the mobile object is performed by using this pair of cameras.
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公开(公告)号：US10660606B2
公开(公告)日：2020-05-26
申请号：US15725918
申请日：2017-10-05
Applicant: SOCIONEXT INC.
Inventor： Naoto Adachi
Abstract: An ultrasonic imaging apparatus includes a plurality of transducers aligned in an array, a select circuit configured to cause transducers selected from the plurality of transducers to transmit an ultrasonic pulse and receive received signals, respectively, and a digital signal processing circuit configured to perform a first operation of adding up an odd number of the received signals, arranged in an order corresponding to the aligned array, with delays that are symmetrical between two sides across a center that is a centrally located signal, and to perform a second operation of adding up an even number of the received signals, arranged in an order corresponding to the aligned array, with delays that are symmetrical between two sides across a center that is situated between two centrally located signals.
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公开(公告)号：US10658355B2
公开(公告)日：2020-05-19
申请号：US16565380
申请日：2019-09-09
Applicant: SOCIONEXT INC.
Inventor： Shiro Usami
IPC: H01L23/52 , H01L27/02 , H01L29/87 , H01L29/861 , H01L23/528
Abstract: Diffusion regions having the same conductivity type are arranged on a side of a second wiring and a side of a third wiring, respectively under a first wiring connected to a signal terminal. Diffusion regions are separated in a whole part or one part of a range in a Y direction. That is, under first wiring, diffusion regions are only formed in parts opposed to diffusion regions formed under the second wiring and third wiring connected to a power supply terminal or a ground terminal, and a diffusion region is not formed in a central part in an X direction. Therefore, terminal capacity of the signal terminal can be reduced without causing ESD resistance to be reduced, in an ESD protection circuit with the signal terminal.
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公开(公告)号：US10658293B2
公开(公告)日：2020-05-19
申请号：US16232370
申请日：2018-12-26
Applicant: SOCIONEXT INC.
Inventor： Tomoyuki Kirimura
IPC: H01L23/528 , H01L27/118 , G06F30/00 , G06F30/394 , H01L23/522 , H01L23/58 , H01L27/02 , H01L27/092 , H01L29/78 , H01L29/775 , H01L21/768 , H01L21/02 , H01L21/265 , H01L21/311 , H01L21/321 , H01L21/8238 , H01L23/532 , H01L29/167
Abstract: A semiconductor device having a plurality of first wirings (X-direction) which include a first power supply line and a second power supply line, a plurality of third wirings (X-direction) which include a third (fourth) power supply line that is located above the first (second) power supply line and is electrically connected to the first (second) power supply line. The semiconductor device also has a plurality of second wirings (Y-direction) that include a first (second) connection wiring located above the first (second) power supply line and below the third (fourth) power supply line that is electrically connected to the first (second) power supply line and to the third (fourth) power supply line.
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公开(公告)号：US10651175B2
公开(公告)日：2020-05-12
申请号：US16245164
申请日：2019-01-10
Applicant: SOCIONEXT INC.
Inventor： Hiroyuki Shimbo
IPC: H01L27/092 , H01L27/02 , H01L27/06 , H01L27/088 , H01L29/66
Abstract: Disclosed herein is a semiconductor device including two standard cells which are arranged adjacent to each other in an X direction. One of the two standard cells includes a plurality of first fins which extend in the X direction, and which are arranged along a boundary between the two standard cells in a Y direction. The other standard cell includes a plurality of second fins which extend in the X direction, and which are arranged along the boundary between the two standard cells in the Y direction. The plurality of second fins includes a dummy fin.
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Patent Agency Ranking
公开(公告)号：US10608616B2
公开(公告)日：2020-03-31
申请号：US16244002
申请日：2019-01-09
Applicant: SOCIONEXT INC.
Inventor： Charles Joseph Dedic
IPC: H03K3/017 , H03K3/012 , H03K5/05 , H03K5/135 , G06F1/06 , G06F1/10 , H03K5/01 , H03M1/12 , H03K5/00 , H03M1/66
Abstract: Clock distribution circuitry comprising: a plurality of first buffers and second buffers, the first and second buffers being inverting buffers; and control circuitry configured to generate first, second, third and fourth control signals for bulk-voltage control of transistors of the buffers, the control circuitry configured to control at least one of the first to fourth control signals as a variable signal.
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公开(公告)号：US10593702B2
公开(公告)日：2020-03-17
申请号：US16110203
申请日：2018-08-23
Applicant: SOCIONEXT INC.
Inventor： Masaki Tamaru , Kazuyuki Nakanishi , Hidetoshi Nishimura
IPC: H01L27/02 , H01L27/092 , H01L27/118 , H01L21/8238
Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.
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公开(公告)号：US20200076442A1
公开(公告)日：2020-03-05
申请号：US16410793
申请日：2019-05-13
Applicant: SOCIONEXT INC.
Inventor： Hassan SHAFEEU , Vlad CRETU , Nicolas RIVAT
Abstract: Current-generation circuitry, comprising: a plurality of candidate current sources operable to generate respective candidate currents; an output current source operable to generate an output current; comparator circuitry; and control circuitry operable to control the current sources and the comparator circuitry to: in an adjustment step, generate an adjustment current by selecting one of the candidate currents or by summing together a plurality of the candidate currents, and calibrate at least a plurality of the candidate current sources; and in a calibration step, following the adjustment step, generate a reference current by selecting one of the candidate currents generated by the candidate current sources calibrated in the adjustment step or by summing together a plurality of the candidate currents generated by those candidate current sources, and calibrate the output current source by comparing its output current to that reference current and adjusting a control signal applied to that output current source.
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公开(公告)号：US20200064206A1
公开(公告)日：2020-02-27
申请号：US16674928
申请日：2019-11-05
Applicant: Socionext Inc.
Inventor： Hiroyuki HAMANO , Takashi MIYAZAKI
Abstract: A temperature measuring device includes first and second semiconductor elements each of which has a p-n junction, a transistor group including a plurality of transistors of which respective sources are connected to a power source and of which respective gates are connected to each other, the plurality of transistors constituting a current source, the transistor group being configured to output a first current and a second current having a different magnitude from the first current to the first and second semiconductor elements, respectively, and a selector configured to select at least one first transistor and a plurality of second transistors different from the first transistor, from among the plurality of transistors.
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公开(公告)号：US20200042029A1
公开(公告)日：2020-02-06
申请号：US16600123
申请日：2019-10-11
Applicant: SOCIONEXT INC.
Inventor： Kyota SHIMIZU , Toshiya SUZUKI , Tomohiko KOTO
IPC: G05F1/618 , H03K19/00 , H03K19/0175 , H03K3/356 , H03K19/003 , G11C7/10 , H03K3/281
Abstract: An output circuit includes: a first p-type transistor having a source connected to VDDH and a gate to which an input signal is fed; and a second p-type transistor having a source connected to the drain of the first p-type transistor, a drain connected to an output terminal, and a gate connected to a first node. A capacitor has one terminal to which the input signal is fed and the other terminal connected to the first node. A first n-type transistor has a source connected to VDDL, a drain connected to the first node, and a gate to which a signal corresponding to the input signal is fed. A second n-type transistor has a source and a gate both connected to VDDL and a drain connected to the first node.
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