公开(公告)号：US12033715B2

公开(公告)日：2024-07-09

申请号：US18063041

申请日：2022-12-07

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana ,  Arpit Vijayvergia

IPC: G11C7/00 ,  G11C7/06 ,  H03K19/20

CPC classification number: G11C7/06 ,  H03K19/20

Abstract: The present disclosure is directed to arranging user data memory cells and test memory cells in a configurable memory array that can perform both differential and single ended read operations during memory start-up and normal memory use, respectively. Different arrangements of the user data memory cells and the test memory cells in the memory array result in increased effectiveness of memory array, in terms of area optimization, memory read accuracy and encryption for data security.

公开(公告)号：US20240213101A1

公开(公告)日：2024-06-27

申请号：US18535882

申请日：2023-12-11

Applicant: STMicroelectronics International N.V.

Inventor： Brice ARRAZAT ,  Christian RIVERO

IPC: H01L21/8238 ,  H01L21/762 ,  H01L27/092

CPC classification number: H01L21/823878 ,  H01L21/76224 ,  H01L27/092

Abstract: An electronic circuit includes a plurality of transistors including: at least one first MOS transistor of a first conductivity type arranged inside and on top of at least one first active area of a semiconductor substrate and at least one second MOS transistor of the second conductivity type arranged inside and on top of at least one second active area of the semiconductor substrate. Each first active area is delimited by a first insulating region which is recessed with respect to a first surface of the semiconductor substrate by a first depth. Each second active area is delimited by a second insulating region which is flush with the first surface of the semiconductor substrate, or which is recessed with respect to the first surface of the semiconductor substrate by a second depth smaller than the first depth.

公开(公告)号：US20240205611A1

公开(公告)日：2024-06-20

申请号：US18066148

申请日：2022-12-14

Applicant: STMicroelectronics International N.V.

Inventor： Domenico GIUSTI ,  Fabio QUAGLIA ,  Marco FERRERA ,  Carlo Luigi PRELINI

IPC: H04R17/00

CPC classification number: H04R17/00

Abstract: The present disclosure is directed to transducer assemblies or device in which one or more buried cavities are present within a substrate and define or form one or more membranes along a surface of the substrate. One or more piezoelectric actuators are formed on the one or more membranes and the one or more piezoelectric actuators drive the membranes at an operating frequency with an operating bandwidth of the transducer assemblies. Each of the one or more membranes is anchored at respective portions to a main body portion of the substrate to provide robust and strong anchoring of each of the one or more membranes to push unwanted flexure modes outside the operating bandwidth of the transducer assemblies.

公开(公告)号：US20240204686A1

公开(公告)日：2024-06-20

申请号：US18526547

申请日：2023-12-01

Applicant: STMicroelectronics International N.V.

Inventor： Vincent BINET

IPC: H02M7/53846 ,  H02M7/538 ,  H02M7/5388

CPC classification number: H02M7/538466 ,  H02M7/53803 ,  H02M7/5388

Abstract: According to one aspect, an integrated circuit is provided comprising: a digital-to-analog converter (MDAC) configured to convert a digital word (DIGW) into an analog signal (SDAC), a switching circuit including: a first transistor (PMOS1) having a drain configured to receive the analog signal (SDAC) and a source connected to a drain of a second transistor (PMOS2) and a third transistor (NMOS1) having a drain configured to receive the analog signal (SDAC) and a source connected to a drain of a fourth transistor (NMOS2); a voltage control circuit configured to apply a voltage on the source of the first transistor (PMOS1) and on the source of the third transistor (NMOS1) so as to limit a drain-source voltage of the first transistor (PMOS1) and a drain-source voltage of the third transistor (NMOS1) regardless of the value of said digital word.

公开(公告)号：US20240199415A1

公开(公告)日：2024-06-20

申请号：US18084811

申请日：2022-12-20

Applicant: STMicroelectronics International N.V.

Inventor： Federico VERCESI ,  Andrea NOMELLINI ,  Paolo FERRARI

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00285 ,  B81B7/0038 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2203/0315 ,  B81B2207/07 ,  B81C2201/0109 ,  B81C2201/0132 ,  B81C2201/0178 ,  B81C2203/0118

Abstract: Disclosed herein is a process flow for forming a MEMS IMU including an accelerometer and a gyroscope each located in a separate sealed cavity maintained at a different pressure. Formation of the MEMS IMU includes the use of a first vHF release to etch a sacrificial layer underneath a structural layer containing the accelerometer and gyroscope and capping the device under formation to set both cavities at a first pressure. The floor of one of the cavities is formed to including a gas permeable layer. Formation further includes forming a chimney underneath the gas permeable layer and then performing a second vHF release to etch through the gas permeable layer and expose the cavity containing the gas permeable layer so that its pressure may be set to be different than that of the other cavity when the chimney is sealed.

公开(公告)号：US12008200B1

公开(公告)日：2024-06-11

申请号：US18169000

申请日：2023-02-14

Applicant: STMicroelectronics International N.V.

Inventor： Kien Beng Tan

IPC: G06F3/041 ,  G06F3/044

CPC classification number: G06F3/04184 ,  G06F3/0446

Abstract: A method for operating a touch sensing panel includes a touchscreen controller determining a first plurality of excitation signals in accordance with a first plurality of codes, wherein a sum of the first plurality of codes is a sequence of numbers having a same absolute value and signs alternating between adjacent numbers in the sequence of numbers. The method further includes the touchscreen controller transmitting each of the first plurality of excitation signals to a respective transmitting (TX) touch sensor of the touch sensing panel simultaneously during a first time frame. The method further includes the touchscreen controller determining touch strengths in accordance with a first plurality of output signals received by a plurality of receiving (RX) touch sensors of the touch sensing panel during the first time frame.

公开(公告)号：US20240186991A1

公开(公告)日：2024-06-06

申请号：US18443112

申请日：2024-02-15

Applicant: STMicroelectronics International N.V.

Inventor： Manoj Kumar TIWARI ,  Saiyid Mohammad Irshad RIZVI

IPC: H03K3/037 ,  H03K3/13

CPC classification number: H03K3/0377 ,  H03K3/037 ,  H03K3/13

Abstract: An integrated circuit includes an input pad and a Schmitt trigger coupled to the input pad. The Schmitt trigger includes a first inverter and a second inverter. The Schmitt trigger includes a pull-up transistor coupled to an input of the second inverter and configure to supply a high reference voltage to the input of the second inverter.

公开(公告)号：US20240186195A1

公开(公告)日：2024-06-06

申请号：US18529064

申请日：2023-12-05

Applicant: STMicroelectronics International N.V.

Inventor： Laurent HERARD ,  Olivier ZANELLATO ,  Patrick LAURENT

IPC: H01L23/10 ,  H01L21/48 ,  H01L21/52 ,  H01L23/00 ,  H01L23/053 ,  H01L23/498

CPC classification number: H01L23/10 ,  H01L21/4846 ,  H01L21/52 ,  H01L23/053 ,  H01L23/49816 ,  H01L24/97 ,  H01L2224/97

Abstract: An integrated circuit package includes a support substrate having a mounting face and a lateral wall having an inner face and an outer face. The inner face delimits with the mounting face a cavity. The outer face includes a step extending outwardly of the package. An electronic chip disposed in the cavity and electrically connected to electrically-conductive contact pads. A sealing structure is bonded by a glue to an upper face of the lateral wall to seal the cavity. The glue does not spill out over the outer face of the lateral wall. Electrically-conductive connection elements are located over a lower face of the support substrate and electrically cooperate with the contact pads through an interconnection network located in the support substrate.

公开(公告)号：US20240179036A1

公开(公告)日：2024-05-30

申请号：US18059103

申请日：2022-11-28

Applicant: STMicroelectronics International N.V.

Inventor： Iztok BRATUZ ,  Vinko KUNC ,  Maksimiljan STIGLIC

IPC: H04L25/49

CPC classification number: H04L25/4904

Abstract: Various embodiments of the present disclosure disclose decoding techniques for mitigating data corruption due to duty cycle distortion, jitter, and other distortions to a digital signal. Decoding processes, apparatuses, and systems are provided that utilize a decoding framework for improving the accuracy of output bit streams generated from digital signals. An example process receives data indicative of a digital signal, generates a signal measurement for the digital signal that includes signal length descriptive between a two rising edges of a digital signal or two falling edges of the demodulated digital signal, and generates at least one portion of an output bit stream for the digital signal based at least in part on the signal measurement.

公开(公告)号：US20240170960A1

公开(公告)日：2024-05-23

申请号：US18512292

申请日：2023-11-17

Applicant: STMicroelectronics International N.V.

Inventor： Francois TAILLIET

IPC: H02H9/04

CPC classification number: H02H9/046

Abstract: An ESD protection circuit includes a first voltage limiter having a first input terminal electrically coupled to each first signal pad of an integrated circuit by a first diode mounted in reverse bias during the integrated circuit operation. The first voltage limiter is mounted to be conductive between each first signal pad and ground during a positive ESD on the first signal pad. A second voltage limiter is electrically coupled and mounted to be conductive in the same direction as the first voltage limiter, between an external power supply pad and ground. An internal node outputs an internal power supply voltage to the domain, and is passed through by a current in response to a positive ESD on the power supply pad which is lower than the current passing through the first voltage limiter. A blocking diode is electrically connected between the first input terminal and the power supply pad.