公开(公告)号：US20040027488A1

公开(公告)日：2004-02-12

申请号：US10420532

申请日：2003-04-22

Applicant: STMicroelectronics S.r.I.

Inventor： Giuseppe Messina ,  Sebastiano Battiato ,  Massimo Mancuso

IPC: H04N009/74

CPC classification number: G06T3/4076

Abstract: A method for obtaining a high-resolution digital image from a plurality of starting images formed by pixel matrices acquired at a lower resolution includes combining the plurality of starting images to generate a provisional high-resolution image, and producing from the provisional high-resolution image a plurality of low-resolution images. Each low-resolution image corresponds to a respective starting image. At least a portion of the provisional high-resolution image is processed by modifying pixels thereof to reduce a difference between the plurality of starting images and the plurality of low-resolution images. The processing includes associating with the pixels of the provisional high-resolution image a respective uncertainty measure representing an uncertainty of the pixels, and leaving unmodified at least a subset of the pixels of the provisional high-resolution image having associated therewith a respective uncertainty measure smaller than a threshold.

Abstract translation: 从通过以较低分辨率获取的像素矩阵形成的多个起始图像中获得高分辨率数字图像的方法包括组合多个起始图像以生成临时高分辨率图像，并从临时高分辨率图像 多个低分辨率图像。 每个低分辨率图像对应于相应的起始图像。 临时高分辨率图像的至少一部分通过修改其像素来处理，以减少多个起始图像与多个低分辨率图像之间的差异。 该处理包括将临时高分辨率图像的像素与表示像素的不确定性的各自的不确定性度量相关联，并且使具有相关联的临时高分辨率图像的至少一个子集的相关不确定性度量留下未修改的至少一个子集 超过门槛。

公开(公告)号：US20040008539A1

公开(公告)日：2004-01-15

申请号：US10434395

申请日：2003-05-07

Applicant: STMicroelectronics S.r.I.

Inventor： Luigi Pascucci

IPC: G11C016/04 ,  G11C029/00

CPC classification number: G11C14/00

Abstract: A non-volatile latch circuit includes a first, volatile information-storage element; a second, non-volatile information-storage element electrically programmable and associated with the first element; first circuit means activatable for operatively coupling the second element to the first element, the first circuit means being activated for loading into the first element an information stored in the second element. The circuit additionally includes second circuit means associated with the first element for setting the first element in a select state; third circuit means associated with the second element and driven by the first element for selectively enabling the programming of the second element depending on the state of the first element.

Abstract translation: 非易失性锁存电路包括第一易失性信息存储元件; 电可编程并与第一元件相关联的第二非易失性信息存储元件; 第一电路装置可激活以将第二元件可操作地耦合到第一元件，第一电路装置被激活以将第一元件中存储的信息加载到第一元件中。 电路还包括与第一元件相关联的用于将第一元件设置在选择状态的第二电路装置; 与第二元件相关联并由第一元件驱动的第三电路装置，用于根据第一元件的状态选择性地启用第二元件的编程。

公开(公告)号：US20040008090A1

公开(公告)日：2004-01-15

申请号：US10406628

申请日：2003-04-03

Applicant: STMicroelectronics S.r.I.

Inventor： Paolo Rolandi

IPC: H03B001/00

CPC classification number: H03K3/0315 ,  H03L7/00

Abstract: An adjustable frequency oscillator circuit includes: an odd number of inverters connected so as to form a loop; a plurality of capacitive elements each connected to an output terminal of a respective inverter; and an output terminal, which supplies a signal oscillating at an oscillating frequency. The oscillator circuit further includes a calibration circuit for calibrating maximum currents which can be delivered by the inverters to the respective capacitive elements.

Abstract translation: 可变频振荡电路包括：奇数个反相器连接成一个环路; 多个电容元件，各自连接到各个逆变器的输出端子; 以及输出端子，其提供以振荡频率振荡的信号。 振荡器电路还包括校准电路，用于校准可由反相器传送到各个电容元件的最大电流。

公开(公告)号：US20030235097A1

公开(公告)日：2003-12-25

申请号：US10449761

申请日：2003-05-30

Applicant: STMicroelectronics S.r.I.

Inventor： Emilio Camerlenghi ,  Paolo Cappelletti ,  Tecla Ghilardi ,  Mauro Sali ,  Giorgio Servalli

IPC: G11C007/00

CPC classification number: G11C29/006 ,  G11C16/04 ,  G11C29/02 ,  G11C29/50 ,  G11C2029/5002

Abstract: An integrated non-volatile memory device may include a first matrix of memory cells organized into rows (or word lines) and columns (or bit lines), corresponding row and column decoding circuits, and read, modify and erase circuits for reading and modifying data stored in the memory cells. Furthermore, the memory device may also include a test structure including a second matrix of memory cells smaller than the first. The second memory matrix may include word line couplings each having a different contact to gate distance. That is, each coupling is aligned a different distance from its respective gate than adjacent couplings.

Abstract translation: 集成的非易失性存储器件可以包括组织成行（或字线）和列（或位线），对应的行和列解码电路的存储器单元的第一矩阵，以及用于读取和修改数据的读取，修改和擦除电路 存储在存储单元中。 此外，存储器件还可以包括测试结构，其包括小于第一存储器单元的存储器单元的第二矩阵。 第二存储器矩阵可以包括每个具有与栅极距离的不同接触的字线耦合。 也就是说，每个联轴器与相应的门相比不同于相邻联接器的距离。

公开(公告)号：US20030227987A1

公开(公告)日：2003-12-11

申请号：US10395040

申请日：2003-03-21

Applicant: STMicroelectronics S.r.I.

Inventor： Vanni Poletto ,  Paolo Ghigini

IPC: H04L007/02

CPC classification number: H03M5/12 ,  H04L25/4904

Abstract: A method and a corresponding decoder for decoding a Manchester encoded binary data signal includes receiving the Manchester encoded binary data signal having a first sequence of central bit transitions and a second sequence of initial bit transitions. A local clock signal is generated, and the central bit transitions of the Manchester encoded binary data signal are determined. Determination of the central bit transitions includes measuring the time interval elapsing between a pair adjacent central bit transitions, expressed as a number N of cycles of the local clock signal, and selecting each successive central bit transition based upon the time interval N measured between the pair of central bit transitions which immediately precede the successive central bit transition.

Abstract translation: 用于解码曼彻斯特编码的二进制数据信号的方法和相应的解码器包括接收具有第一中心位转换序列的曼彻斯特编码的二进制数据信号和第二个初始位转换序列。 产生本地时钟信号，并确定曼彻斯特编码的二进制数据信号的中心位转换。 确定中心位转换包括测量在相邻的中央位转换之间经过的时间间隔，表示为本地时钟信号的周期数N，并且基于在该对之间测量的时间间隔N来选择每个连续的中央位转换 的中心位转换，紧接在连续的中央位转换之前。

公开(公告)号：US20030214346A1

公开(公告)日：2003-11-20

申请号：US10374762

申请日：2003-02-24

Applicant: STMicroelectronics S.r.I.

Inventor： Roberto Pelliconi

IPC: G05F003/02

CPC classification number: H02M3/073 ,  H02M2003/071 ,  H02M2003/077

Abstract: A charge pump for negative voltages, having at least one stage including a high-voltage terminal and a low-voltage terminal; a first branch and a second branch, which are symmetrical and are connected between the high-voltage terminal and the low-voltage terminal and each of which comprises a respective first transistor and a respective second transistor. The first and the second transistors are all triple-well MOS transistors of one and the same polarity type.

Abstract translation: 一种用于负电压的电荷泵，具有包括高压端子和低压端子的至少一个级; 第一分支和第二分支，其对称并且连接在高压端子和低压端子之间，并且每个分别包括相应的第一晶体管和相应的第二晶体管。 第一和第二晶体管都是同一极性类型的三阱MOS晶体管。

公开(公告)号：US20030210585A1

公开(公告)日：2003-11-13

申请号：US10390556

申请日：2003-03-14

Applicant: STMicroelectronics S.r.I.

Inventor： Oreste Bernardi ,  Marco Redaelli ,  Corrado Villa

IPC: G11C007/00

CPC classification number: G11C16/10 ,  G11C2216/20 ,  G11C2216/22

Abstract: A non-volatile memory device is proposed. The non-volatile memory device includes a flash memory and means for executing external commands, the external commands including a first subset of commands for accessing the flash memory directly; the memory device further includes a programmable logic unit and means for storing program code for the logic unit, the external commands including a second subset of at least one command for causing the logic unit to process information stored in at least one portion of the flash memory under the control of the program code.

Abstract translation: 提出了一种非易失性存储器件。 非易失性存储器件包括闪速存储器和用于执行外部命令的装置，所述外部命令包括用于直接访问闪速存储器的第一命令子集; 存储器件还包括可编程逻辑单元和用于存储用于逻辑单元的程序代码的装置，外部命令包括用于使逻辑单元处理存储在闪速存储器的至少一部分中的信息的至少一个命令的第二子集 在程序代码的控制下。

公开(公告)号：US20030189504A1

公开(公告)日：2003-10-09

申请号：US10384493

申请日：2003-03-06

Applicant: STMicroelectronics S.r.I.

Inventor： Vittorio Colonna ,  Andrea Baschirotto ,  Gabriele Gandolfi

IPC: H03M003/00

CPC classification number: H03M3/338 ,  H03M1/0663 ,  H03M3/464

Abstract: A sigma-delta-type converter comprises: a sigma-delta modulator having a digital output having a first prefixed bit number; a randomizer including a circular memory; an analogical reconstruction filter comprising a branch number equal to said first default number including sampling capacitors and a low-pass filter; characterized in that said circular memory comprises a number of elements equal to said first default number of bits less one and receives in input said first default number of bits less one, and in that a bit of said first default number of bits is applied to one of said branches of said reconstruction filter.

Abstract translation: Σ-Δ型转换器包括：具有第一前缀位数的数字输出的Σ-Δ调制器; 包括循环存储器的随机化器; 模拟重构滤波器，包括等于包括采样电容器和低通滤波器的所述第一默认数字的分支数; 其特征在于，所述循环存储器包括等于所述第一默认位数小于等于的数量的元素，并且在输入中接收所述第一默认位数少于1的元素，并且所述第一默认位数的位被应用于一个 的所述重建滤波器的分支。

公开(公告)号：US20030127701A1

公开(公告)日：2003-07-10

申请号：US10319441

申请日：2002-12-13

Applicant: STMicroelectronics S.r.I.

Inventor： Roberto Tiziani ,  Carlo Passagrilli

IPC: H01L031/00

CPC classification number: H01L24/05 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05083 ,  H01L2224/05118 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12036 ,  H01L2924/14 ,  H01L2924/20755 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A semiconductor electronic device includes a die of semiconductor material and a support. The die of semiconductor material includes an integrated electronic circuit and a plurality of contact pads associated with the electronic circuit and connected electrically to the support by wire leads. Each contact pad may include a lower layer of aluminum, copper, or alloys thereof, and an upper layer including at least one film of a metal and/or metallic alloy including nickel, palladium, or alloys thereof, and being deposited by an electroless chemical process.

Abstract translation: 半导体电子器件包括半导体材料的裸片和支持体。 半导体材料的管芯包括集成电子电路和与电子电路相关联的多个接触焊盘，并且通过引线电连接到支撑件。 每个接触垫可以包括铝，铜或其合金的下层，以及包括至少一种包含镍，钯或其合金的金属和/或金属合金膜的上层，并通过无电化学材料 处理。

公开(公告)号：US20030113981A1

公开(公告)日：2003-06-19

申请号：US10284031

申请日：2002-10-29

Applicant: STMicroelectronics S.r.I.

Inventor： Chantal Combi ,  Matteo Fiorito ,  Marta Mottura ,  Giuseppe Visalli ,  Benedetto Vigna

IPC: H01L021/00 ,  H01L021/76

CPC classification number: H01L21/764 ,  H01L21/76208 ,  H01L21/76229 ,  H01L27/08

Abstract: A process for manufacturing a semiconductor wafer integrating electronic devices and a structure for electromagnetic decoupling are disclosed. The method includes providing a wafer of semiconductor material having a substrate; forming a plurality of first mutually adjacent trenches, open on a first face of the wafer, which have a depth and a width and define walls); by thermal oxidation, completely oxidizing the walls and filling at least partially the first trenches, so as to form an insulating structure of dielectric material; and removing one portion of the substrate comprised between the insulating structure and a second face of the wafer, opposite to the first face of the wafer.

Abstract translation: 公开了一种用于制造集成电子器件的半导体晶片和用于电磁去耦的结构的工艺。 该方法包括提供具有基板的半导体材料晶片; 形成多个第一相互相邻的沟槽，在晶片的第一面上开口，其具有深度和宽度并限定壁）; 通过热氧化，完全氧化壁并至少部分地填充第一沟槽，以形成介电材料的绝缘结构; 以及移除所述绝缘结构和所述晶片的与所述晶片的第一面相对的第二面之间的衬底的一部分。