中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

155 records (took 0.02 seconds)

    PARTITIONABLE DATA BUS
    121.
    发明申请
    PARTITIONABLE DATA BUS 有权
    可分区数据总线

    公开(公告)号：US20150026511A1

    公开(公告)日：2015-01-22

    申请号：US14016610

    申请日：2013-09-03

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Gabriel H. Loh ,  Yi Xu ,  James M. O'Connor

    IPC: G06F11/07

    CPC classification number: G06F11/0727 ,  G06F11/2007 ,  G06F2201/85

    Abstract: A method and a system are provided for partitioning a system data bus. The method can include partitioning off a portion of a system data bus that includes one or more faulty bits to form a partitioned data bus. Further, the method includes transferring data over the partitioned data bus to compensate for data loss due to the one or more faulty bits in the system data bus.

    Abstract translation: 提供了一种分区系统数据总线的方法和系统。 该方法可以包括分离包括一个或多个故障位的系统数据总线的一部分以形成分区数据总线。 此外，该方法包括在分区数据总线上传送数据以补偿由于系统数据总线中的一个或多个错误位导致的数据丢失。

    MEMORY HIERARCHY USING ROW-BASED COMPRESSION
    122.
    发明申请
    MEMORY HIERARCHY USING ROW-BASED COMPRESSION 有权
    使用基于ROW的压缩的内存分层

    公开(公告)号：US20150019813A1

    公开(公告)日：2015-01-15

    申请号：US13939377

    申请日：2013-07-11

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Gabriel H. Loh ,  James M. O'Connor

    IPC: G06F12/08

    CPC classification number: G06F12/0866 ,  G06F12/0895 ,  G06F2212/1024 ,  G06F2212/1036 ,  G06F2212/401

    Abstract: A system includes a first memory and a device coupleable to the first memory. The device includes a second memory to cache data from the first memory. The second memory includes a plurality of rows, each row including a corresponding set of compressed data blocks of non-uniform sizes and a corresponding set of tag blocks. Each tag block represents a corresponding compressed data block of the row. The device further includes decompression logic to decompress data blocks accessed from the second memory. The device further includes compression logic to compress data blocks to be stored in the second memory.

    Abstract translation: 系统包括第一存储器和可耦合到第一存储器的装置。 该设备包括用于缓存来自第一存储器的数据的第二存储器。 第二存储器包括多行，每行包括对应的一组非均匀尺寸的压缩数据块和相应的一组标签块。 每个标签块表示该行的对应的压缩数据块。 该设备还包括解压缩逻辑以解压缩从第二存储器访问的数据块。 该设备还包括压缩逻辑以压缩要存储在第二存储器中的数据块。

    CACHE COHERENCY USING DIE-STACKED MEMORY DEVICE WITH LOGIC DIE
    123.
    发明申请
    CACHE COHERENCY USING DIE-STACKED MEMORY DEVICE WITH LOGIC DIE 有权
    使用带LOGO DIE的堆叠式存储器设备进行高速缓存

    公开(公告)号：US20140181417A1

    公开(公告)日：2014-06-26

    申请号：US13726146

    申请日：2012-12-23

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Gabriel H. Loh ,  Bradford M. Beckmann ,  Lisa R. Hsu ,  Michael Ignatowski ,  Michael J. Schulte

    IPC: G06F12/08

    CPC classification number: G06F12/0828 ,  G11C5/025 ,  G11C8/12 ,  G11C29/12 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/1461 ,  H01L2924/15311 ,  Y02D10/13 ,  H01L2924/00

    Abstract: A die-stacked memory device implements an integrated coherency manager to offload cache coherency protocol operations for the devices of a processing system. The die-stacked memory device includes a set of one or more stacked memory dies and a set of one or more logic dies. The one or more logic dies implement hardware logic providing a memory interface and the coherency manager. The memory interface operates to perform memory accesses in response to memory access requests from the coherency manager and the one or more external devices. The coherency manager comprises logic to perform coherency operations for shared data stored at the stacked memory dies. Due to the integration of the logic dies and the memory dies, the coherency manager can access shared data stored in the memory dies and perform related coherency operations with higher bandwidth and lower latency and power consumption compared to the external devices.

    Abstract translation: 堆叠堆叠的存储器件实现集成的一致性管理器以卸载处理系统的设备的高速缓存一致性协议操作。 芯片堆叠的存储器件包括一组一个或多个堆叠的存储器管芯和一组一个或多个逻辑管芯。 一个或多个逻辑模块实现提供存储器接口和一致性管理器的硬件逻辑。 存储器接口操作以响应来自一致性管理器和一个或多个外部设备的存储器访问请求来执行存储器访问。 相关性管理器包括对存储在堆叠存储器管芯上的共享数据执行一致性操作的逻辑。 由于逻辑管芯和存储器管芯的集成，一致性管理器可以访问存储在存储器管芯中的共享数据，并且与外部器件相比具有更高带宽和更低的延迟和功耗的相关一致性操作。

    HYBRID CACHE
    124.
    发明申请
    HYBRID CACHE 有权
    混合高速缓存

    公开(公告)号：US20140181387A1

    公开(公告)日：2014-06-26

    申请号：US13724669

    申请日：2012-12-21

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Matthew R. Poremba ,  Gabriel H. Loh

    IPC: G11C7/10 ,  G06F12/12

    CPC classification number: G11C7/1072 ,  G06F12/0886 ,  G06F2212/1041 ,  G06F2212/601

    Abstract: Data caching methods and systems are provided. A method is provided for a hybrid cache system that dynamically changes modes of one or more cache rows of a cache between an un-split mode having a first tag field and a first data field to a split mode having a second tag field, a second data field being smaller than the first data field and a mapped page field to improve the cache access efficiency of a workflow being executed in a processor. A hybrid cache system is provided in which the cache is configured to operate one or more cache rows in an un-split mode or in a split mode. The system is configured to dynamically change modes of the cache rows from the un-split mode to the split mode to improve the cache access efficiency of a workflow being executed by the processor.

    Abstract translation: 提供数据缓存方法和系统。 提供了一种用于混合高速缓存系统的方法，其将具有第一标签字段和第一数据字段的未分割模式之间的高速缓存行的一个或多个高速缓存行的模式动态地改变为具有第二标签字段的分割模式，第二标记字段 数据字段小于第一数据字段和映射页面字段，以提高在处理器中正在执行的工作流的高速缓存访​​问效率。 提供了混合高速缓存系统，其中高速缓存被配置为以未分割模式或分离模式操作一个或多个高速缓存行。 该系统被配置为将缓存行的模式从未分割模式动态地改变到分割模式，以提高由处理器执行的工作流的高速缓存访​​问效率。

    PARITY DATA MANAGEMENT FOR A MEMORY ARCHITECTURE
    125.
    发明申请
    PARITY DATA MANAGEMENT FOR A MEMORY ARCHITECTURE 有权
    用于存储器架构的奇偶性数据管理

    公开(公告)号：US20140173378A1

    公开(公告)日：2014-06-19

    申请号：US13720504

    申请日：2012-12-19

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： James M. O'Connor ,  Vilas K. Sridharan ,  Gabriel H. Loh

    IPC: H03M13/11

    CPC classification number: H03M13/11 ,  G06F11/00 ,  G06F11/1048 ,  H03M13/05

    Abstract: A processor system as presented herein includes a processor core, cache memory coupled to the processor core, a memory controller coupled to the cache memory, and a system memory component coupled to the memory controller. The system memory component includes a plurality of independent memory channels configured to store data blocks, wherein the memory controller controls the storing of parity bits in at least one of the plurality of independent memory channels. In some implementations, the system memory is realized as a die-stacked memory component.

    Abstract translation: 如本文所述的处理器系统包括处理器核心，耦合到处理器核心的高速缓存存储器，耦合到高速缓冲存储器的存储器控​​制器以及耦合到存储器控制器的系统存储器组件。 系统存储器组件包括被配置为存储数据块的多个独立存储器通道，其中存储器控制器控制在多个独立存储器通道中的至少一个中存储奇偶校验位。 在一些实现中，系统存储器被实现为管芯堆叠的存储器组件。

    Tracking Non-Native Content in Caches
    126.
    发明申请
    Tracking Non-Native Content in Caches 审中-公开
    跟踪缓存中的非本地内容

    公开(公告)号：US20140156941A1

    公开(公告)日：2014-06-05

    申请号：US13691375

    申请日：2012-11-30

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Gabriel H. Loh ,  Mithuna S. Thottehodi ,  Yasuko Eckert ,  James M. O'Connor ,  Mauricio Breternitz ,  Bradford M. Beckmann ,  Nuwan Jayasena

    IPC: G06F12/08

    CPC classification number: G06F12/0895 ,  G06F1/3275 ,  G06F12/0811 ,  G06F12/0846 ,  G06F12/126 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/502 ,  Y02D10/124 ,  Y02D10/13 ,  Y02D10/14

    Abstract: The described embodiments include a cache with a plurality of banks that includes a cache controller. In these embodiments, the cache controller determines a value representing non-native cache blocks stored in at least one bank in the cache, wherein a cache block is non-native to a bank when a home for the cache block is in a predetermined location relative to the bank. Then, based on the value representing non-native cache blocks stored in the at least one bank, the cache controller determines at least one bank in the cache to be transitioned from a first power mode to a second power mode. Next, the cache controller transitions the determined at least one bank in the cache from the first power mode to the second power mode.

    Abstract translation: 所描述的实施例包括具有包括高速缓存控制器的多个存储体的高速缓存。 在这些实施例中，高速缓存控制器确定表示存储在高速缓存中的至少一个存储区中的非本机高速缓存块的值，其中当高速缓存块的归属位于相对于预定位置时，高速缓存块对于存储体是非本地的 去银行。 然后，高速缓存控制器基于代表存储在至少一个存储体中的非本地高速缓存块的值，确定高速缓存中的至少一个存储体将从第一功率模式转换到第二功率模式。 接下来，高速缓存控制器将所确定的高速缓存中的至少一个存储体从第一功率模式转换到第二功率模式。

    Victim Row Refreshes for Memories in Electronic Devices
    130.
    发明申请
    Victim Row Refreshes for Memories in Electronic Devices 有权

    公开(公告)号：US20220415384A1

    公开(公告)日：2022-12-29

    申请号：US17360958

    申请日：2021-06-28

    Applicant: Advanced Micro Devices, Inc.

    Inventor： SeyedMohammad SeyedzadehDelcheh ,  Gabriel H. Loh

    IPC: G11C11/406 ,  G11C11/4076

    Abstract: An electronic device includes a memory having a plurality of memory rows and a memory refresh functional block that performs a victim row refresh operation. For the victim row refresh operation, the memory refresh functional block selects one or more victim memory rows that may be victims of data corruption caused by repeated memory accesses in a specified group of memory rows near each of the one or more victim memory rows. The memory refresh functional block then individually refreshes each of the one or more victim memory rows.

Patent Agency Ranking