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165 条记录 (耗时 0.035 秒)

    CMOS transistors with stressed high mobility channels
    121.
    发明授权
    CMOS transistors with stressed high mobility channels 有权
    具有应力高移动性通道的CMOS晶体管

    公开(公告)号：US08354694B2

    公开(公告)日：2013-01-15

    申请号：US12855738

    申请日：2010-08-13

    申请人： Stephen W. Bedell ,  Jee H. Kim ,  Siegfried L. Maurer ,  Alexander Reznicek ,  Devendra K. Sadana

    发明人： Stephen W. Bedell ,  Jee H. Kim ,  Siegfried L. Maurer ,  Alexander Reznicek ,  Devendra K. Sadana

    IPC分类号： H01L29/66

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/7843 ,  H01L29/7848

    摘要： A p-type field effect transistor (PFET) having a compressively stressed channel and an n-type field effect transistor (NFET) having a tensilely stressed channel are formed. In one embodiment, a silicon-germanium alloy is employed as a device layer, and the source and drain regions of the PFET are formed employing embedded germanium-containing regions, and source and drain regions of the NFET are formed employing embedded silicon-containing regions. In another embodiment, a germanium layer is employed as a device layer, and the source and drain regions of the PFET are formed by implanting a Group IIIA element having an atomic radius greater than the atomic radius of germanium into portions of the germanium layer, and source and drain regions of the NFET are formed employing embedded silicon-germanium alloy regions. The compressive stress and the tensile stress enhance the mobility of charge carriers in the PFET and the NFET, respectively.

    摘要翻译： 形成具有压应力通道的p型场效应晶体管（PFET）和具有拉伸应力通道的n型场效应晶体管（NFET）。 在一个实施例中，使用硅 - 锗合金作为器件层，并且使用嵌入的含锗区域形成PFET的源极和漏极区域，并且使用嵌入的含硅区域形成NFET的源极和漏极区域 。 在另一个实施例中，锗层用作器件层，PFET的源极和漏极区通过将原子半径大于锗的原子半径的IIIA族元素注入到锗层的部分中而形成， 使用嵌入式硅 - 锗合金区域形成NFET的源极和漏极区域。 压应力和拉伸应力分别提高了PFET和NFET中载流子的迁移率。

    QUASI-HYDROPHOBIC Si-Si WAFER BONDING USING HYDROPHILIC Si SURFACES AND DISSOLUTION OF INTERFACIAL BONDING OXIDE
    127.
    发明申请
    QUASI-HYDROPHOBIC Si-Si WAFER BONDING USING HYDROPHILIC Si SURFACES AND DISSOLUTION OF INTERFACIAL BONDING OXIDE 有权
    使用水解硅表面和界面结合氧化物的溶解度的偶氮硅Si-Si波形粘结

    公开(公告)号：US20090298258A1

    公开(公告)日：2009-12-03

    申请号：US12538115

    申请日：2009-08-08

    申请人： Joel P. de Souza ,  John A. Ott ,  Alexander Reznicek ,  Devendra K. Sadana ,  Katherine L. Saenger

    发明人： Joel P. de Souza ,  John A. Ott ,  Alexander Reznicek ,  Devendra K. Sadana ,  Katherine L. Saenger

    IPC分类号： H01L21/30

    CPC分类号： H01L21/187 ,  H01L21/76251

    摘要： The present invention provides a method for removing or reducing the thickness of ultrathin interfacial oxides remaining at Si—Si interfaces after silicon wafer bonding. In particular, the invention provides a method for removing ultrathin interfacial oxides remaining after hydrophilic Si—Si wafer bonding to create bonded Si—Si interfaces having properties comparable to those achieved with hydrophobic bonding. Interfacial oxide layers of order of about 2 to about 3 nm are dissolved away by high temperature annealing, for example, an anneal at 1300°-1330° C. for 1-5 hours. The inventive method is used to best advantage when the Si surfaces at the bonded interface have different surface orientations, for example, when a Si surface having a (100) orientation is bonded to a Si surface having a (110) orientation. In a more general aspect of the invention, the similar annealing processes may be used to remove undesired material disposed at a bonded interface of two silicon-containing semiconductor materials. The two silicon-containing semiconductor materials may be the same or different in surface crystal orientation, microstructure (single-crystal, polycrystalline, or amorphous), and composition.

    摘要翻译： 本发明提供一种在硅晶片接合之后去除或减少残留在Si-Si界面处的超薄界面氧化物的厚度的方法。 特别地，本发明提供了一种去除在亲水性Si-Si晶片接合之后残留的超薄界面氧化物以产生具有与通过疏水性接合实现的性能相当的特性的结合Si-Si界面的方法。 约2至约3nm的界面氧化物层通过高温退火（例如1300°-1330℃退火1-5小时）被溶解掉。 当粘合界面处的Si表面具有不同的表面取向时，例如当具有（100）取向的Si表面被结合到具有（110）取向的Si表面时，本发明的方法被用于最好的优点。 在本发明的更一般的方面中，类似的退火工艺可用于去除设置在两个含硅半导体材料的键合界面处的不期望的材料。 两种含硅半导体材料在表面晶体取向，微结构（单晶，多晶或无定形）和组成上可以相同或不同。

    Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer
    128.
    发明授权
    Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer 失效
    通过掩埋的p +硅锗层的阳极氧化应变的绝缘体上硅

    公开(公告)号：US07592671B2

    公开(公告)日：2009-09-22

    申请号：US11620663

    申请日：2007-01-06

    申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

    发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

    IPC分类号： H01L29/94

    CPC分类号： H01L21/76259 ,  Y10S438/967

    摘要： A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.

    摘要翻译： 提供了制造应变半导体绝缘体（SSOI）衬底的成本有效和可制造的方法，其避免晶片接合。 该方法包括在衬底上生长各种外延半导体层，其中半导体层中的至少一个是在应变半导体层下面的掺杂和弛豫半导体层; 通过电解阳极氧化处理将掺杂和松弛的半导体层转化成多孔半导体，并氧化以将多孔半导体层转化为掩埋氧化物层。 该方法提供了在衬底上包括松弛半导体层的SSOI衬底; 在松弛的半导体层上形成高质量的掩埋氧化物层; 以及在高质量掩埋氧化物层上的应变半导体层。 根据本发明，松弛半导体层和应变半导体层具有相同的晶体取向。

    STRAINED SEMICONDUCTOR-ON-INSULATOR BY Si:C COMBINED WITH POROUS PROCESS
    129.
    发明申请
    STRAINED SEMICONDUCTOR-ON-INSULATOR BY Si:C COMBINED WITH POROUS PROCESS 有权
    通过与多孔工艺组合的Si：C的应变半导体绝缘体

    公开(公告)号：US20090117720A1

    公开(公告)日：2009-05-07

    申请号：US11934479

    申请日：2007-11-02

    申请人： Stephen W. Bedell ,  Joel P. de Souza ,  Alexander Reznicek ,  Devendra K. Sadana

    发明人： Stephen W. Bedell ,  Joel P. de Souza ,  Alexander Reznicek ,  Devendra K. Sadana

    IPC分类号： H01L21/36

    CPC分类号： H01L21/76245 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02258 ,  H01L21/02337 ,  H01L21/3167

    摘要： A method of fabricating a strained semiconductor-on-insulator (SSOI) substrate is provided. The method includes first providing a structure that includes a substrate, a doped and relaxed semiconductor layer on the substrate, and a strained semiconductor layer on the doped and relaxed semiconductor layer. In the invention, the doped and relaxed semiconductor layer having a lower lattice parameter than the substrate. Next, at least the doped and relaxed semiconductor layer is converted into a buried porous layer and the structure including the buried porous layer is annealed to provide a strained semiconductor-on-insulator substrate. During the annealing, the buried porous layer is converted into a buried oxide layer.

    摘要翻译： 提供了制造应变半导体绝缘体（SSOI）衬底的方法。 该方法包括首先提供包括衬底，衬底上的掺杂和弛豫半导体层以及掺杂和弛豫半导体层上的应变半导体层的结构。 在本发明中，掺杂和松弛的半导体层具有比衬底更低的晶格参数。 接下来，至少将掺杂和松弛的半导体层转换成掩埋多孔层，并且将包括埋入多孔层的结构退火以提供应变绝缘体上半导体衬底。 在退火过程中，将埋入的多孔层转化为掩埋氧化物层。