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    VARIABLE-RESISTANCE MATERIAL MEMORIES, PROCESSES OF FORMING SAME, AND METHODS OF USING SAME
    121.
    发明申请
    VARIABLE-RESISTANCE MATERIAL MEMORIES, PROCESSES OF FORMING SAME, AND METHODS OF USING SAME 有权
    可变电阻材料，其形成方法和使用方法

    公开(公告)号：US20130130469A1

    公开(公告)日：2013-05-23

    申请号：US13739616

    申请日：2013-01-11

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu

    IPC: H01L21/8239

    CPC classification number: H01L21/8239 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/75 ,  H01L27/101 ,  H01L27/1052 ,  H01L27/24

    Abstract: A variable-resistance material memory array includes a series of variable-resistance material memory cells. The series of variable-resistance material memory cells can be arranged in parallel with a corresponding series of control gates. A select gate can also be disposed in series with the variable-resistance material memory cells. Writing/reading/erasing to a given variable-resistance material memory cell can include turning off the corresponding control gate, while turning on all other control gates. Various devices can include such a variable-resistance material memory array.

    Abstract translation: 可变电阻材料存储器阵列包括一系列可变电阻材料存储单元。 一系列可变电阻材料存储单元可以与相应的一系列控制栅极并联布置。 选择栅极也可以与可变电阻材料存储单元串联布置。 对给定的可变电阻材料存储单元的写入/读取/擦除可以包括在打开所有其它控制栅极的同时关闭对应的控制栅极。 各种装置可以包括这种可变电阻材料存储器阵列。

    CONFINED CELL STRUCTURES AND METHODS OF FORMING CONFINED CELL STRUCTURES
    122.
    发明公开
    CONFINED CELL STRUCTURES AND METHODS OF FORMING CONFINED CELL STRUCTURES 审中-公开

    公开(公告)号：US20240237546A1

    公开(公告)日：2024-07-11

    申请号：US18615422

    申请日：2024-03-25

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Gurtej Sandhu

    IPC: H10N50/10 ,  G11C11/16 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

    CPC classification number: H10N50/10 ,  G11C11/161 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

    Abstract: Techniques for reducing damage in memory cells are provided. Memory cell structures are typically formed using dry etch and/or planarization processes which damage certain regions of the memory cell structure. In one or more embodiments, certain regions of the cell structure may be sensitive to damage. For example, the free magnetic region in magnetic memory cell structures may be susceptible to demagnetization. Such regions may be substantially confined by barrier materials during the formation of the memory cell structure, such that the edges of such regions are protected from damaging processes. Furthermore, in some embodiments, a memory cell structure is formed and confined within a recess in dielectric material.

    METHODS FOR FORMING NARROW VERTICAL PILLARS AND INTEGRATED CIRCUIT DEVICES HAVING THE SAME
    123.
    发明申请
    METHODS FOR FORMING NARROW VERTICAL PILLARS AND INTEGRATED CIRCUIT DEVICES HAVING THE SAME 审中-公开

    公开(公告)号：US20200350496A1

    公开(公告)日：2020-11-05

    申请号：US16934844

    申请日：2020-07-21

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Kunal Parekh

    IPC: H01L45/00 ,  H01L27/24

    Abstract: In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some embodiments, the openings can contain phase change material to form a phase change memory cell. The openings occupied by the pillars can be defined using crossing lines of sacrificial material, e.g., spacers, that are formed on different vertical levels. The lines of material can be formed by deposition processes that allow the formation of very thin lines. Exposed material at the intersection of the lines is selectively removed to form the openings, which have dimensions determined by the widths of the lines. The openings can be filled, for example, with phase change material.

    Variable resistance memory with lattice array using enclosing transistors
    125.
    发明授权
    Variable resistance memory with lattice array using enclosing transistors 有权

    公开(公告)号：US10109347B2

    公开(公告)日：2018-10-23

    申请号：US14940386

    申请日：2015-11-13

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Jun Liu

    IPC: G11C13/00 ,  G11C5/06 ,  G11C11/40 ,  H01L27/24 ,  H01L45/00 ,  G11C11/4097

    Abstract: A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are grounded or biased at the same voltage. A top electrode select line that is in contact with the selected variable resistance memory element is selected. The word line having the word line transistors surrounding the selected variable resistance memory element are turned on to supply programming current to the element. Current flows from the selected top electrode select line through the variable resistance memory element into the common source/drain region of the surrounding word line transistors, across the transistors to the nearest bitline contacts. The word lines are patterned in various lattice configurations.

    Arrays Of Memory Cells And Methods Of Forming An Array Of Memory Cells
    126.
    发明申请
    Arrays Of Memory Cells And Methods Of Forming An Array Of Memory Cells 有权

    公开(公告)号：US20180122859A1

    公开(公告)日：2018-05-03

    申请号：US15852275

    申请日：2017-12-22

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Kunal R. Parekh

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2463 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

    Abstract: An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced along the buried access lines. The pillars individually include a memory cell. Outer access lines are elevationally outward of the pillars and the buried access lines. The outer access lines are of higher electrical conductivity than the buried access lines. A plurality of conductive vias is spaced along and electrically couple pairs of individual of the buried and outer access lines. A plurality of the pillars is between immediately adjacent of the vias along the pairs. Electrically conductive metal material is directly against tops of the buried access lines and extends between the pillars along the individual buried access lines. Other embodiments, including method, are disclosed.

    Arrays Of Memory Cells And Methods Of Forming An Array Of Memory Cells
    130.
    发明申请
    Arrays Of Memory Cells And Methods Of Forming An Array Of Memory Cells 审中-公开

    公开(公告)号：US20170092695A1

    公开(公告)日：2017-03-30

    申请号：US15375507

    申请日：2016-12-12

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Kunal R. Parekh

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2463 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

    Abstract: An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced along the buried access lines. The pillars individually include a memory cell. Outer access lines are elevationally outward of the pillars and the buried access lines. The outer access lines are of higher electrical conductivity than the buried access lines. A plurality of conductive vias is spaced along and electrically couple pairs of individual of the buried and outer access lines. A plurality of the pillars is between immediately adjacent of the vias along the pairs. Electrically conductive metal material is directly against tops of the buried access lines and extends between the pillars along the individual buried access lines. Other embodiments, including method, are disclosed.

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