公开(公告)号：US20210335751A1

公开(公告)日：2021-10-28

申请号：US17372476

申请日：2021-07-11

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A method to construct a 3D system, the method including: providing a base wafer; transferring a first memory wafer on top of the base wafer; thinning the first memory wafer, thus forming a thin first memory wafer; transferring a second memory wafer on top of the thin first memory wafer; thinning the second memory wafer, thus forming a thin second memory wafer; and transferring a memory control wafer on top of the thin second memory wafer; where the transferring a memory control wafer includes bonding of the memory control wafer to the thin second memory wafer, and where the bonding includes oxide to oxide and conductor to conductor bonding.

公开(公告)号：US11152386B2

公开(公告)日：2021-10-19

申请号：US16483431

申请日：2018-02-03

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

IPC: H01L29/76 ,  H01L27/11556 ,  H01L21/28 ,  H01L27/11582 ,  H01L29/423

Abstract: A 3D memory device, the device including: a first vertical pillar; a second vertical pillar, where the first vertical pillar and the second vertical pillar function as a source or a drain for a plurality of overlaying horizontally-oriented memory transistors, where the plurality of overlaying horizontally-oriented memory transistors are self-aligned being formed following the same lithography step; and memory control circuits, where the memory control circuits are disposed at least partially directly underneath the plurality of overlaying horizontally-oriented memory transistors, or are disposed at least partially directly above the plurality of overlaying horizontally-oriented memory transistors.

公开(公告)号：US20210313345A1

公开(公告)日：2021-10-07

申请号：US17346295

申请日：2021-06-14

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  G11C7/18

Abstract: A 3D memory device, the device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of bit-line pillars, where each bit-line pillar of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the bit-line pillars are vertically oriented, where the channel is horizontally oriented, and where the channel is isolated from another channel disposed directly above the channel.

公开(公告)号：US10991675B2

公开(公告)日：2021-04-27

申请号：US16337665

申请日：2017-09-19

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H01L23/52 ,  H01L25/065 ,  H01L25/18 ,  H01L21/683 ,  H01L25/00 ,  H01L25/16 ,  H01L27/06 ,  G11C11/56 ,  G11C16/14 ,  G11C16/10 ,  H01L21/822 ,  H01L27/11597 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11524 ,  G11C29/00

Abstract: A method to construct a 3D system, the method including: providing a base wafer; and then transferring a first memory wafer on top of the base wafer; and then thinning the first memory wafer; and then transferring a second memory wafer on top of the first memory wafer; and then thinning the second memory wafer; and transferring a memory control on top of the second memory wafer; and then thinning the memory control, where the first memory wafer includes a cut-layer, and where the thinning of the first memory wafer includes using the cut-layer to control the thickness of the first memory wafer.

公开(公告)号：US20200185372A1

公开(公告)日：2020-06-11

申请号：US16786060

申请日：2020-02-10

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A 3D semiconductor device, the device including: a first level including first single crystal transistors; and a second level including second single crystal transistors, where the first level is overlaid by the second level, where a vertical distance from the first single crystal transistors to the second single crystal transistors is less than four microns, where the first level includes a plurality of processors, and where the second level includes a plurality of memory cells.

公开(公告)号：US20180350823A1

公开(公告)日：2018-12-06

申请号：US15990611

申请日：2018-05-26

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H01L27/112 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11529 ,  H01L27/11573 ,  H01L23/48

CPC classification number: H01L27/11286 ,  G11C5/025 ,  G11C13/0023 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C17/165 ,  G11C2213/71 ,  H01L23/481 ,  H01L27/10802 ,  H01L27/1104 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/24

Abstract: A multilevel semiconductor device including: a first level including a first array of first memory cells and first control line; a second level including a second array of second memory cells and second control line; a third level including a third array of third memory cells and third control line, where the second level overlays the first, and where the third level overlays the second; a first, second and third access pillar; memory control circuits designed to individually control cells of the first, second and third memory cells, where the device includes an array of units, where each of the units includes a plurality of the first, second and third memory cells, and a portion of the memory control circuits, where the array of units include at least eight rows and eight columns of units, and where the memory control is designed to control independently each of the units.

公开(公告)号：US10014318B2

公开(公告)日：2018-07-03

申请号：US15333138

申请日：2016-10-24

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H01L27/115 ,  H01L27/11582 ,  H01L29/47 ,  H01L29/78 ,  H01L29/167 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/02 ,  H01L27/11514

CPC classification number: H01L27/11582 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/11514 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/11578 ,  H01L29/167 ,  H01L29/47 ,  H01L29/7827 ,  H01L29/792

Abstract: A multilevel semiconductor device, including: a first level including a first array of first memory cells; a second level including a second array of second memory cells, the first level is overlaid by the second level, where at least one of the first memory cells includes a vertically oriented first transistor, and where at least one of the second memory cells includes a vertically oriented second transistor, and where the first transistor includes a first single crystal channel, and where the second transistor includes a second single crystal channel, and where the first transistor is self-aligned to the second transistor.

公开(公告)号：US09953994B2

公开(公告)日：2018-04-24

申请号：US15344562

申请日：2016-11-06

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H01L27/115 ,  H01L27/11568 ,  H01L27/11565 ,  H01L29/792 ,  G11C16/04 ,  G11C14/00 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  H01L29/78 ,  G11C11/56

CPC classification number: H01L27/11568 ,  G11C11/5621 ,  G11C14/0018 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  H01L27/11565 ,  H01L28/00 ,  H01L29/7831 ,  H01L29/792 ,  H01L29/7923

Abstract: A semiconductor device, including: a plurality of non-volatile memory cells including a first memory cell and a second memory cell, where the plurality of non-volatile memory cells includes source diffusion lines and drain diffusion lines, at least one of the source diffusion lines and drain diffusion lines are shared by the first memory cell and the second memory cell, where the first memory cell includes a thin tunneling oxide of less than 1 nm thickness, and where the second memory cell includes a thick tunneling oxide of greater than 2 nm thickness.

公开(公告)号：US20170117291A1

公开(公告)日：2017-04-27

申请号：US15333138

申请日：2016-10-24

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H01L27/115 ,  H01L27/02 ,  H01L29/167 ,  H01L23/528 ,  H01L29/47 ,  H01L29/78

CPC classification number: H01L27/11582 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/11514 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/11578 ,  H01L29/167 ,  H01L29/47 ,  H01L29/7827 ,  H01L29/792

Abstract: A multilevel semiconductor device, including: a first level including a first array of first memory cells; a second level including a second array of second memory cells, the first level is overlaid by the second level, where at least one of the first memory cells includes a vertically oriented first transistor, and where at least one of the second memory cells includes a vertically oriented second transistor, and where the first transistor includes a first single crystal channel, and where the second transistor includes a second single crystal channel, and where the first transistor is self-aligned to the second transistor.