公开(公告)号：US09482964B2

公开(公告)日：2016-11-01

申请号：US14279039

申请日：2014-05-15

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Chia-Chang Hsu ,  Yi-Ting Chen ,  Teng-Chin Kuo ,  Chun-Chi Yu

IPC: G03F7/20

CPC classification number: G03F7/70516

Abstract: An overlap mark set is provided to have at least a first and a second overlap marks both of which are located at the same pattern layer. The first overlap mark includes at least two sets of X-directional linear patterns, having a preset offset a1 therebetween; and at least two sets of Y-directional linear patterns, having the preset offset a1 therebetween. The second overlap mark includes at least two sets of X-directional linear patterns, having a preset offset b1 therebetween; and at least two sets of Y-directional linear patterns, having the preset offset b1 therebetween. The preset offsets a1 and b1 are not equal.

Abstract translation: 提供重叠标记集以具有两个位于相同图案层的至少第一和第二重叠标记。 第一重叠标记包括至少两组X方向线性图案，其间具有预置偏移量a1; 以及至少两组Y方向线性图案，其间具有预设偏移量a1。 第二重叠标记包括至少两组X方向线性图案，其间具有预设偏移量b1; 以及至少两组Y方向线性图案，其间具有预设的偏移量b1。 预置偏移量a1和b1不相等。

公开(公告)号：US20160315008A1

公开(公告)日：2016-10-27

申请号：US15176142

申请日：2016-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung ,  En-Chiuan Liou

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76831 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/485 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: A semiconductor device includes a semiconductor structure, a plurality of gate structures, at least one source/drain structure, at least one trench, a dielectric pattern, and a conductive structure. The gate structures are disposed on the semiconductor structure. The source/drain structure is disposed between two adjacent gate structures. The trench is disposed between the two adjacent gate structures and corresponding to the source/drain structure. The dielectric pattern is disposed on sidewalls of the trench. The conductive structure is disposed in the trench and electrically connected to the source/drain structure. The conductive structure includes a first portion surrounded by the dielectric pattern and a second portion connected to the source/drain structure, and the first portion is disposed on the second portion. A width of the first portion is smaller than a width of the second portion.

Abstract translation: 半导体器件包括半导体结构，多个栅极结构，至少一个源极/漏极结构，至少一个沟槽，电介质图案和导电结构。 栅极结构设置在半导体结构上。 源极/漏极结构设置在两个相邻栅极结构之间。 沟槽设置在两个相邻栅极结构之间并对应于源极/漏极结构。 电介质图案设置在沟槽的侧壁上。 导电结构设置在沟槽中并电连接到源极/漏极结构。 导电结构包括被电介质图案包围的第一部分和连接到源极/漏极结构的第二部分，第一部分设置在第二部分上。 第一部分的宽度小于第二部分的宽度。

公开(公告)号：US20160293725A1

公开(公告)日：2016-10-06

申请号：US14704994

申请日：2015-05-06

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L29/42376 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/4232 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method for manufacturing a semiconductor device having metal gate includes following steps. A substrate is provided. At least a transistor including a dummy gate is formed on the substrate and the transistor is embedded in an interlayer dielectric (ILD) layer. A first removal process is performed to remove a portion of the dummy gate to form a first recess in the transistor. An etching process is subsequently performed to remove a portion of the ILD layer to widen the first recess and to form a widened first recess. A second removal process is subsequently performed to remove the dummy gate entirely and to form a second recess in the transistor. A metal gate is formed in the second recess and followed by forming an insulating cap layer on the metal gate.

Abstract translation: 一种制造具有金属栅极的半导体器件的方法包括以下步骤。 提供基板。 在衬底上形成至少包括伪栅极的晶体管，并且将晶体管嵌入在层间电介质层（ILD）层中。 执行第一去除处理以去除伪栅极的一部分以在晶体管中形成第一凹部。 随后进行蚀刻处理以去除ILD层的一部分以加宽第一凹部并形成加宽的第一凹部。 随后执行第二去除处理以完全去除伪栅极并在晶体管中形成第二凹槽。 在第二凹部中形成金属栅极，然后在金属栅极上形成绝缘盖层。

公开(公告)号：US20160284641A1

公开(公告)日：2016-09-29

申请号：US14692762

申请日：2015-04-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Chih-Sen Huang ,  Yu-Cheng Tung

IPC: H01L23/522 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/033 ,  H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/3085 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L29/00 ,  H01L29/66545 ,  H01L29/66553

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate having a gate structure thereon and a first interlayer dielectric (ILD) layer surrounding the gate structure; a first hard mask on the gate structure; and a second hard mask on the gate structure, wherein the first hard mask is adjacent to two sides of the second hard mask and the first hard mask and the first hard mask comprises silicon nitride.

Abstract translation: 公开了一种半导体器件。 半导体器件包括：其上具有栅极结构的衬底和围绕栅极结构的第一层间电介质（ILD）层; 栅极结构上的第一个硬掩模; 以及栅极结构上的第二硬掩模，其中所述第一硬掩模与所述第二硬掩模的两侧相邻，并且所述第一硬掩模和所述第一硬掩模包括氮化硅。

公开(公告)号：US09455135B2

公开(公告)日：2016-09-27

申请号：US14562768

申请日：2014-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  En-Chiuan Liou ,  Chieh-Te Chen

IPC: H01L21/302 ,  H01L21/02 ,  H01L21/311 ,  H01L21/033 ,  H01L21/027

CPC classification number: H01L21/0206 ,  H01L21/02186 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer around the gate structure; forming a hard mask on the gate structure and the ILD layer; forming a first patterned mask layer on the hard mask; using the first patterned mask layer to remove part of the hard mask for forming a patterned hard mask; and utilizing a gas to strip the first patterned mask layer while forming a protective layer on the patterned hard mask, wherein the gas is selected from the group consisting of N2 and O2.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上至少具有栅极结构的衬底和围绕栅极结构的层间电介质（ILD）层; 在栅极结构和ILD层上形成硬掩模; 在硬掩模上形成第一图案化掩模层; 使用第一图案化掩模层去除用于形成图案化硬掩模的硬掩模的一部分; 并且利用气体剥离第一图案化掩模层，同时在图案化的硬掩模上形成保护层，其中气体选自N2和O2。

公开(公告)号：US20160268142A1

公开(公告)日：2016-09-15

申请号：US14683120

申请日：2015-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/311 ,  H01L21/3115 ,  H01L21/3105 ,  H01L21/033

CPC classification number: H01L21/0337 ,  H01L21/3086

Abstract: A manufacturing method of a patterned structure of a semiconductor device includes following steps. A plurality of support features are formed on a substrate. A first conformal spacer layer is formed on the support features and a surface of the substrate, a second conformal spacer layer is formed on the first conformal spacer layer, and a covering layer is formed on the second conformal spacer layer. A gap between the support features is filled with the first conformal spacer layer, the second conformal spacer layer, and the covering layer. A first process is performed to remove a part of the covering layer, the second conformal spacer layer, and the first conformal spacer layer. A second process is performed to remove the support features or the first conformal spacer layer between the support feature and the second conformal spacer layer to expose a part of the surface of the substrate.

Abstract translation: 半导体器件的图案化结构的制造方法包括以下步骤。 在基板上形成多个支撑特征。 第一共形间隔层形成在支撑特征和基板的表面上，在第一共形间隔层上形成第二共形间隔层，并且在第二共形间隔层上形成覆盖层。 支撑特征之间的间隙填充有第一共形间隔层，第二共形间隔层和覆盖层。 执行第一处理以去除覆盖层，第二共形间隔层和第一共形间隔层的一部分。 执行第二过程以移除支撑特征和第二共形间隔层之间的支撑特征或第一共形间隔层，以暴露基底表面的一部分。

公开(公告)号：US20160247678A1

公开(公告)日：2016-08-25

申请号：US14629491

申请日：2015-02-24

Applicant: United Microelectronics Corp.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Hon-Huei Liu ,  An-Chi Liu ,  Chih-Wei Wu ,  Jyh-Shyang Jenq ,  Shih-Fang Hong ,  En-Chiuan Liou ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Chih-Kai Hsu ,  Mei-Chen Chen ,  Chia-Hsun Tseng

IPC: H01L21/033 ,  H01L21/66

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823431 ,  H01L22/12

Abstract: A method of forming a semiconductor structure includes following steps. First of all, a patterned hard mask layer having a plurality of mandrel patterns is provided. Next, a plurality of first mandrels is formed on a substrate through the patterned hard mask. Following these, at least one sidewall image transferring (SIT) process is performed. Finally, a plurality of fins is formed in the substrate, wherein each of the fins has a predetermined critical dimension (CD), and each of the mandrel patterns has a CD being 5-8 times greater than the predetermined CD.

Abstract translation: 形成半导体结构的方法包括以下步骤。 首先，提供具有多个心轴图案的图案化的硬掩模层。 接下来，通过图案化的硬掩模在基板上形成多个第一心轴。 接下来，执行至少一个侧壁图像传送（SIT）处理。 最后，在基板上形成多个散热片，其中每个翅片具有预定的临界尺寸（CD），并且每个心轴图案具有比预定CD大5-8倍的CD。

公开(公告)号：US09397008B1

公开(公告)日：2016-07-19

申请号：US14691586

申请日：2015-04-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung ,  En-Chiuan Liou

IPC: H01L21/8234 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L21/027

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76831 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/485 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: A manufacturing method of a conductive structure in a semiconductor device includes the following steps. A plurality of gate structures are formed on a semiconductor structure, and a first dielectric layer is formed in space between the gate structures. A first process is then performed to remove at least a part of the first dielectric layer in the space between the gate structures. A second dielectric layer is then formed and covers the gate structures so as to form at least one air void in the space between the gate structures. A second process is performed to form at least one opening penetrating the second dielectric layer and exposing the air void. The air void exposed by the opening is then filled with at least one conductive material for forming a conductive structure between the gate structures.

Abstract translation: 半导体器件中的导电结构的制造方法包括以下步骤。 在半导体结构上形成多个栅极结构，并且在栅极结构之间的空间中形成第一介电层。 然后执行第一处理以去除栅极结构之间的空间中的第一介电层的至少一部分。 然后形成第二电介质层并覆盖栅极结构，以便在栅极结构之间的空间中形成至少一个空气空隙。 执行第二过程以形成穿透第二电介质层并暴露空气空隙的至少一个开口。 然后用至少一个导电材料填充由开口暴露的空气孔，用于在栅极结构之间形成导电结构。

公开(公告)号：US09385236B1

公开(公告)日：2016-07-05

申请号：US14748240

申请日：2015-06-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ying Sun ,  En-Chiuan Liou ,  Ming-Shing Chen ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  G06F17/50

CPC classification number: H01L29/7853 ,  G06F17/5081 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/7856

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a plurality of fin shaped structures and a dummy gate structure. The fin shaped structures are disposed in a substrate, where at least one of the fin shaped structures has a tipped end. The dummy gate structure is disposed on the substrate, and includes an extending portion covering the tipped end.

Abstract translation: 半导体器件及其形成方法，半导体器件包括多个鳍状结构和虚拟栅极结构。 翅片状结构设置在基板中，其中至少一个翅片形结构具有尖端。 虚拟栅极结构设置在基板上，并且包括覆盖端部的延伸部分。

公开(公告)号：US20160190019A1

公开(公告)日：2016-06-30

申请号：US15060572

申请日：2016-03-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  Yu-Ru Yang ,  En-Chiuan Liou

IPC: H01L21/8238 ,  H01L29/423 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

Abstract: The present invention provides a method of forming an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.

Abstract translation: 本发明提供一种形成包括衬底，第一晶体管，第二晶体管和第三晶体管的集成电路的方法。 第一晶体管具有包括第一底部阻挡层，第一功函数金属层和第一金属层的第一金属栅极。 第二晶体管具有包括第二底部阻挡层，第二功函数金属层和第二金属层的第二金属栅极。 第三晶体管具有包括第三底部阻挡层，第三功函数金属层和第三金属层的第三金属栅极。 第一晶体管，第二晶体管和第三晶体管具有相同的导电类型。 第一底部阻挡层的氮浓度>第二底部阻挡层的氮浓度>第三底部阻挡层的氮浓度。