公开(公告)号：US08466050B2

公开(公告)日：2013-06-18

申请号：US12830241

申请日：2010-07-02

申请人： Hanming Wu ,  Chia Hao Lee ,  John Chen

发明人： Hanming Wu ,  Chia Hao Lee ,  John Chen

IPC分类号： H01L21/425

CPC分类号： H01J37/3171 ,  H01J37/3007 ,  H01J2237/055 ,  H01J2237/0825 ,  H01L21/2236 ,  H01L21/26513 ,  H01L29/0847 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for forming a lightly doped drain (LDD) region in a semiconductor substrate. The method includes generating an ion beam of a selected species, and accelerating the ion beam, wherein the accelerated ion beam includes a first accelerated portion and a second accelerated portion. The method further includes deflecting the accelerating ion beam, wherein the first and second accelerated portions are concurrently deflected into a first path trajectory having a first deflected angle and second path trajectory having a second deflected angle. In an embodiment, the first and second path trajectories travel in the same direction, which is perpendicular to the surface region of the semiconductor wafer, and the first deflected angle is greater than the second deflected angle. In an embodiment, the selected species may include an n-type ion comprising phosphorous (P), arsenic (As), or antimony (Sb).

摘要翻译： 一种在半导体衬底中形成轻掺杂漏极（LDD）区域的方法。 该方法包括产生所选物种的离子束并加速离子束，其中加速离子束包括第一加速部分和第二加速部分。 该方法还包括偏转加速离子束，其中第一和第二加速部分同时偏转到具有第一偏转角的第一路径轨迹和具有第二偏转角的第二路径轨迹。 在一个实施例中，第一和第二路径轨迹在与半导体晶片的表面区域垂直的相同方向上行进，并且第一偏转角度大于第二偏转角度。 在一个实施方案中，所选择的物质可​​以包括包含磷（P），砷（As）或锑（Sb）的n型离子。

公开(公告)号：US20120273879A1

公开(公告)日：2012-11-01

申请号：US13436308

申请日：2012-03-30

申请人： Shekar Mallikarjunaswamy ,  John Chen ,  YongZhong Hu

发明人： Shekar Mallikarjunaswamy ,  John Chen ,  YongZhong Hu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7835 ,  H01L29/0692 ,  H01L29/1083 ,  H01L29/161 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66659 ,  H01L29/66681

摘要： In an embodiment, this invention discloses a top-drain lateral diffusion metal oxide field effect semiconductor (TD-LDMOS) device supported on a semiconductor substrate. The TD-LDMOS includes a source electrode disposed on a bottom surface of the semiconductor substrate. The TD-LDMOS further includes a source region and a drain region disposed on two opposite sides of a planar gate disposed on a top surface of the semiconductor substrate wherein the source region is encompassed in a body region constituting a drift region as a lateral current channel between the source region and drain region under the planar gate. The TD-LDMOS further includes at least a trench filled with a conductive material and extending vertically from the body region near the top surface downwardly to electrically contact the source electrode disposed on the bottom surface of the semiconductor substrate.

摘要翻译： 在一个实施例中，本发明公开了一种支撑在半导体衬底上的顶排侧向扩散金属氧化物场效应半导体（TD-LDMOS）器件。 TD-LDMOS包括设置在半导体衬底的底表面上的源电极。 TD-LDMOS还包括设置在设置在半导体衬底的顶表面上的平面栅极的两个相对侧上的源极区域和漏极区域，其中源极区域包围在构成漂移区域的体区域中作为横向电流通道 在平面栅极下面的源极区域和漏极区域之间。 TD-LDMOS还包括至少填充有导电材料并且从顶表面附近的主体区域向下垂直延伸的沟槽，以电接触设置在半导体衬底的底表面上的源电极。

公开(公告)号：US08299494B2

公开(公告)日：2012-10-30

申请号：US12484170

申请日：2009-06-12

申请人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

发明人： Hamza Yilmaz ,  Xiaobin Wang ,  Anup Bhalla ,  John Chen ,  Hong Chang

IPC分类号： H01L29/74 ,  H01L31/111 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/0886 ,  H01L21/26586 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0664 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0676 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/365 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/861 ,  H01L29/8613 ,  H01L29/872 ,  H01L29/8725

摘要： A semiconductor device includes a first semiconductor layer and a second semiconductor layer of opposite conductivity type, a first epitaxial layer of the first conductivity type formed on sidewalls of the trenches, and a second epitaxial layer of the second conductivity type formed on the first epitaxial layer where the second epitaxial layer is electrically connected to the second semiconductor layer. The first epitaxial layer and the second epitaxial layer form parallel doped regions along the sidewalls of the trenches, each having uniform doping concentration. The second epitaxial layer has a first thickness and a first doping concentration and the first epitaxial layer and a mesa of the first semiconductor layer together having a second thickness and a second average doping concentration where the first and second thicknesses and the first doping concentration and second average doping concentrations are selected to achieve charge balance in operation.

摘要翻译： 半导体器件包括第一半导体层和相反导电类型的第二半导体层，形成在沟槽的侧壁上的第一导电类型的第一外延层和形成在第一外延层上的第二导电类型的第二外延层 其中第二外延层电连接到第二半导体层。 第一外延层和第二外延层沿着沟槽的侧壁形成平行的掺杂区域，每个具有均匀的掺杂浓度。 第二外延层具有第一厚度和第一掺杂浓度，第一外延层和第一半导体层的台面一起具有第二厚度和第二平均掺杂浓度，其中第一和第二厚度和第一掺杂浓度和第二掺杂浓度 选择平均掺杂浓度以在操作中实现电荷平衡。

公开(公告)号：US08236651B2

公开(公告)日：2012-08-07

申请号：US12583192

申请日：2009-08-14

申请人： John Chen ,  Il Kwan Lee ,  Hong Chang ,  Wenjun Li ,  Anup Bhalla ,  Hamza Yilmaz

发明人： John Chen ,  Il Kwan Lee ,  Hong Chang ,  Wenjun Li ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L21/8234

CPC分类号： H01L29/7811 ,  H01L21/26586 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

摘要： A method for fabricating a semiconductor device includes forming a plurality of trenches, including applying a first mask, forming a first polysilicon region in at least some of the plurality of trenches, forming a inter-polysilicon dielectric region and a termination protection region, including applying a second mask, forming a second polysilicon region in the at least some of the plurality of trenches, forming a first electrical contact to the first polysilicon region and forming a second electrical contact to the second polysilicon region, including applying a third mask, disposing a metal layer, and forming a source metal region and a gate metal region, including applying a fourth mask.

摘要翻译： 一种制造半导体器件的方法包括形成多个沟槽，包括施加第一掩模，在多个沟槽中的至少一些沟槽中形成第一多晶硅区域，形成多晶硅间介质区域和端接保护区域，包括施加 第二掩模，在所述多个沟槽中的所述至少一些沟槽中形成第二多晶硅区域，形成到所述第一多晶硅区域的第一电接触并且形成到所述第二多晶硅区域的第二电接触，包括施加第三掩模， 金属层，并且形成源极金属区域和栅极金属区域，包括施加第四掩模。

公开(公告)号：US08187939B2

公开(公告)日：2012-05-29

申请号：US12565611

申请日：2009-09-23

申请人： Sung-Shan Tai ,  Hamza Yilmaz ,  Anup Bhalla ,  Hong Chang ,  John Chen

发明人： Sung-Shan Tai ,  Hamza Yilmaz ,  Anup Bhalla ,  Hong Chang ,  John Chen

IPC分类号： H01L21/336 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0869 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor device and a method for making a semiconductor device are disclosed. A trench mask may be applied to a semiconductor substrate, which is etched to form trenches with three different widths. A first conductive material is formed at the bottom of the trenches. A second conductive material is formed over the first conductive material. An insulator layer separates the first and second conductive materials. A first insulator layer is deposited on top of the trenches. A body layer is formed in a top portion of the substrate. A source is formed in the body layer. A second insulator layer is applied on top of the trenches and the source. A contact mask is applied on top of the second insulator layer. Source and gate contacts are formed through the second insulator layer. Source and gate metal are formed on top of the second insulator layer.

摘要翻译： 公开了半导体器件和制造半导体器件的方法。 可以将沟槽掩模施加到半导体衬底，其被蚀刻以形成具有三个不同宽度的沟槽。 第一导电材料形成在沟槽的底部。 在第一导电材料上形成第二导电材料。 绝缘体层分离第一和第二导电材料。 第一绝缘体层沉积在沟槽的顶部。 主体层形成在基板的顶部。 源体形成在体层中。 第二绝缘体层被施加在沟槽和源的顶部上。 接触掩模施加在第二绝缘体层的顶部。 源极和栅极触点通过第二绝缘体层形成。 源极和栅极金属形成在第二绝缘体层的顶部上。

公开(公告)号：US20120129328A1

公开(公告)日：2012-05-24

申请号：US13361486

申请日：2012-01-30

申请人： Hong Chang ,  John Chen ,  Limin Weng ,  Wenjun Li

发明人： Hong Chang ,  John Chen ,  Limin Weng ,  Wenjun Li

IPC分类号： H01L21/329 ,  H01L21/768

CPC分类号： H01L29/7813 ,  H01L29/41766 ,  H01L29/47 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/782 ,  H01L2924/0002 ,  Y10S257/905 ,  H01L2924/00

摘要： A semiconductor device formed on a semiconductor substrate may include a component formed in a contact trench located in an active cell region. The component may comprise a barrier metal deposited on a bottom and portions of sidewalls of the contact trench and a tungsten plug deposited in a remaining portion of the contact trench. The barrier metal may comprise first and second metal layers. The first metal layer may be proximate to the sidewall and the bottom of the contact trench. The first metal layer may include a nitride. The second metal layer may be between the first metal layer and the tungsten plug and between the tungsten plug and the sidewall. The second metal layer covers portions of the sidewalls of not covered by the first metal layer.

摘要翻译： 形成在半导体衬底上的半导体器件可以包括形成在位于活性单元区域中的接触沟槽中的部件。 该部件可以包括沉积在接触沟槽的底部和侧壁的一部分上的阻挡金属和沉积在接触沟槽的剩余部分中的钨丝塞。 阻挡金属可以包括第一和第二金属层。 第一金属层可以靠近接触沟槽的侧壁和底部。 第一金属层可以包括氮化物。 第二金属层可以在第一金属层和钨插塞之间以及钨插塞和侧壁之间。 第二金属层覆盖未被第一金属层覆盖的侧壁的部分。

公开(公告)号：US20110291186A1

公开(公告)日：2011-12-01

申请号：US12802185

申请日：2010-06-01

申请人： Hamza Yilmaz ,  John Chen ,  Daniel Ng ,  Wenjun Li

发明人： Hamza Yilmaz ,  John Chen ,  Daniel Ng ,  Wenjun Li

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L27/088

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/47 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/866 ,  H01L29/872 ,  H01L29/8725

摘要： This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate.

摘要翻译： 本发明公开了一种半导体功率器件，其包括设置在半导体衬底的顶表面附近的多个顶部电端子。 顶部电气端子中的每一个包括在半导体衬底的顶表面附近形成为硅化物接触层的端子接触层。 半导体功率器件的沟槽栅极从半导体衬底的顶表面打开，并且每个沟槽栅极包括被配置为硅化物接触层的硅化物层，硅化物层设置在略微低于 半导体衬底的顶表面围绕沟槽栅极。

公开(公告)号：US08037379B1

公开(公告)日：2011-10-11

申请号：US11469353

申请日：2006-08-31

申请人： Hua Fang ,  John Chen

发明人： Hua Fang ,  John Chen

IPC分类号： G11C29/44 ,  G11C29/50

CPC分类号： G11C29/56 ,  G11C29/56008 ,  G11C2029/0403

摘要： A method for predicting an impact on post-repair yield resulting from manufacturing process modification is described. The method includes receiving bit data representing locations of defective memory cells for a plurality of memory devices. The bit data is modified by removing a selected failure pattern type according to a modification scheme to generate modified bit data. Repairs are simulated on hypothetical memory devices corresponding to the modified bit data, generating a result indicating whether the hypothetical memory device is good or bad. A post-repair yield is then identified and a report is generated indicating the post-repair yield, the post-repair yield representing a number of the plurality of memory devices that would be functional after repair had the plurality of memory devices been manufactured without the selected failure pattern. A method to identify a process providing the best economic benefit is also described.

摘要翻译： 描述了一种用于预测由制造过程修改产生的对修复后产量的影响的方法。 该方法包括接收表示多个存储器件的不良存储器单元的位置的位数据。 通过根据修改方案去除所选择的故障模式类型来修改比特数据，以生成修改的比特数据。 在对应于修改的位数据的假想存储器件上模拟修复，产生指示假想存储器件是好还是坏的结果。 然后识别修复后的产量，并且产生指示修复后产量的报告，修复后产量表示在修理之后可以起作用的多个存储器件的数量，在多个存储器件中没有 选择故障模式。 还描述了一种识别提供最佳经济效益的方法。

公开(公告)号：US20110133258A1

公开(公告)日：2011-06-09

申请号：US13016804

申请日：2011-01-28

申请人： John Chen

发明人： John Chen

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/4236 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66666 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： A semiconductor device formed on a semiconductor substrate having a substrate top surface, includes: a gate trench extending from the substrate top surface into the semiconductor substrate; a gate electrode in the gate trench; a dielectric material disposed over the gate electrode; a body region adjacent to the gate trench; a source region embedded in the body region, at least a portion of the source region extending above the dielectric material; a contact trench that allows contact such as electrical contact between the source region and the body region; and a metal layer disposed over at least a portion of a gate trench opening, at least a portion of the source region, and at least a portion of the contact trench.

摘要翻译： 一种半导体器件，形成在具有衬底顶表面的半导体衬底上，包括：从衬底顶表面延伸到半导体衬底中的栅极沟槽; 栅极沟槽中的栅电极; 设置在所述栅电极上的电介质材料; 与栅极沟槽相邻的体区; 源区域，其嵌入在所述体区中，所述源极区域的至少一部分延伸到所述介电材料之上; 接触沟槽，其允许诸如源极区域和身体区域之间的电接触的接触; 以及设置在栅极沟槽开口的至少一部分，源极区的至少一部分以及接触沟槽的至少一部分之上的金属层。

公开(公告)号：US07857785B2

公开(公告)日：2010-12-28

申请号：US12706463

申请日：2010-02-16

申请人： John Chen

发明人： John Chen

IPC分类号： A61M25/10 ,  B29D22/00 ,  C09K19/38

CPC分类号： C09K19/3852 ,  A61L29/049 ,  A61L29/126 ,  A61M25/1027 ,  C09K19/00 ,  C09K19/3809 ,  C09K19/408 ,  Y10T428/1352 ,  C08L53/00

摘要： A medical device, at least a portion of which is formed from a polymer composition including at least one liquid crystal block copolymer having at least one A block and at least one B block wherein the A block is formed of mesogenic repeat units and the B block is a soft block.

摘要翻译： 一种医疗装置，其至少一部分由聚合物组合物形成，所述聚合物组合物包含至少一种具有至少一个A嵌段和至少一个B嵌段的液晶嵌段共聚物，其中A嵌段由介晶重复单元形成，B嵌段 是一个软块。