公开(公告)号：US20230386903A1

公开(公告)日：2023-11-30

申请号：US18232937

申请日：2023-08-11

申请人： NANYA TECHNOLOGY CORPORATION

发明人： LIANG-PIN CHOU

IPC分类号： H01L21/768 ,  H01L23/528 ,  H10B12/00 ,  H01L23/532

CPC分类号： H01L21/7682 ,  H01L21/76837 ,  H01L23/528 ,  H10B12/485 ,  H10B12/34 ,  H01L23/5329 ,  H01L21/76877 ,  H10B12/315 ,  H10B12/482

摘要： A method for preparing a semiconductor device, includes: forming a first dielectric structure and a second dielectric structure over a semiconductor substrate; forming a conductive material over the first dielectric structure and the second dielectric structure, wherein the conductive material extends into a first opening between the first dielectric structure and the second dielectric structure; partially removing the conductive material to form a first bit line and a second bit line in the first opening; forming a first capacitor contact and a second capacitor contact in the first dielectric structure and the second dielectric structure, respectively; forming a sealing dielectric layer over the first bit line and the second bit line such that an air gap is formed between the sealing dielectric layer and the semiconductor substrate; and forming a first capacitor and a second capacitor over the first capacitor contact and the second capacitor contact, respectively.

公开(公告)号：US20230386842A1

公开(公告)日：2023-11-30

申请号：US18231912

申请日：2023-08-09

申请人： NANYA TECHNOLOGY CORPORATION

发明人： CHENG-HSIANG FAN

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/764 ,  H01L21/308

CPC分类号： H01L21/0337 ,  H01L21/31144 ,  H01L21/76229 ,  H01L21/7682 ,  H01L21/76816 ,  H01L21/764 ,  H01L21/308 ,  H01L21/76885 ,  H01L2221/1036

摘要： The present disclosure provides a semiconductor device structure with fine patterns and a method for forming the semiconductor device structure, which prevents the collapse of the fine patterns. The semiconductor device structure includes a first target structure and a second target structure disposed over a semiconductor substrate. The semiconductor device structure also includes a first spacer element disposed over the first target structure, wherein a topmost point of the first spacer element is between a central line of the first target structure and a central line of the second target structure in a cross-sectional view.

公开(公告)号：US11832441B2

公开(公告)日：2023-11-28

申请号：US17533451

申请日：2021-11-23

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Sheng-Hui Yang

IPC分类号： H01L29/78 ,  H10B12/00 ,  H01L29/66 ,  H01L29/417

CPC分类号： H10B12/36 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

摘要： The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a fin positioned on the substrate, a gate structure positioned on the fin, a pair of source/drain regions positioned on two sides of the fin, a dielectric layer positioned above the drain region and adjacent to the gate structure, and a storage conductive layer positioned on the dielectric layer. The drain region, the dielectric layer and the storage conductive layer form a storage structure.

公开(公告)号：US11832432B2

公开(公告)日：2023-11-28

申请号：US17552736

申请日：2021-12-16

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chuan-Lin Hsiao

IPC分类号： H10B12/00

CPC分类号： H10B12/053 ,  H10B12/34

摘要： The present application provides a method of manufacturing a memory device having several word lines (WL) with reduced leakage. The method includes steps of providing a semiconductor substrate defined with an active area and including an isolation surrounding the active area; forming a first recess extending into the semiconductor substrate and across the active area; forming a first lining portion of a first insulating layer conformal to the first recess; disposing a first conductive material conformal to the first lining portion; forming a first conductive member surrounded by the first conductive material; disposing a second conductive material over the first conductive member to form a first conductive layer enclosing the first conductive member; and forming a first protruding portion of the first insulating layer above the first conductive layer and the first conductive member.

公开(公告)号：US11828797B1

公开(公告)日：2023-11-28

申请号：US17738155

申请日：2022-05-06

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Wu-Der Yang

IPC分类号： G01R1/02 ,  G01R1/04 ,  G01R1/067 ,  G01R1/073 ,  G01R31/26 ,  G01R31/28

CPC分类号： G01R31/2887 ,  G01R1/0433

摘要： A probing device includes a probe station. The probe station has a platform having an opening and a plurality of column members supporting the platform. Each of the plurality of column members has one end connected with the platform and an opposite end connected with a moving part. The probing device also includes a manipulator on the platform and a socket configured to support a DUT. The manipulator has a probe. The moving part is configured to allow the probe station to be moved with respect to the DUT.

公开(公告)号：US20230377885A1

公开(公告)日：2023-11-23

申请号：US17664218

申请日：2022-05-19

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Shing-Yih SHIH

IPC分类号： H01L21/027 ,  H01L21/02 ,  H01L21/768

CPC分类号： H01L21/0273 ,  H01L21/02016 ,  H01L21/02697 ,  H01L21/76897

摘要： A method of manufacturing a semiconductor device includes bonding a first wafer with a second wafer. The second wafer includes a substrate, an isolation structure in the substrate, a transistor on the substrate, and a interconnect structure over the second transistor. A first etching process is performed to form a first via opening and a second via opening in the substrate. The second via opening extends to the isolation structure, and the second via opening is deeper than the first via opening. A second etching process is performed such that the first via opening exposes the substrate. A third etching process is performed such that the first via opening and the second via opening exposes the interconnect structure, and the second via opening penetrates the isolation structure. A first via is formed in the first via opening and a second via is formed in the second via opening.

公开(公告)号：US11824082B2

公开(公告)日：2023-11-21

申请号：US17732742

申请日：2022-04-29

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chih-Wei Huang

IPC分类号： H01G4/008 ,  H01L23/522 ,  H01L49/02

CPC分类号： H01L28/75 ,  H01G4/008 ,  H01L23/5222

摘要： The present application discloses a method for fabricating a semiconductor device with capacitors having a shared electrode. The method includes providing a substrate, forming a first trench in the substrate, doping sidewalls and a bottom surface of the first trench to form a bottom conductive structure, forming a first insulating layer on the bottom conductive structure and in the first trench, forming a shared conductive layer on the first insulating layer, forming a second insulating layer on the shared conductive layer, forming a top conductive layer on the second insulating layer, and forming a connection structure electrically connecting the bottom conductive structure and the top conductive layer. The bottom conductive structure, the first insulating layer, and the shared conductive layer together configure a first capacitor unit. The shared conductive layer, the second insulating layer, and the top conductive layer together configure a second capacitor unit.

公开(公告)号：US11824004B2

公开(公告)日：2023-11-21

申请号：US17679295

申请日：2022-02-24

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Teng-Yen Huang

IPC分类号： H01L23/535 ,  H01L23/532 ,  H01L21/768 ,  H10B12/00

CPC分类号： H01L23/535 ,  H01L21/7682 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76895 ,  H01L23/5329 ,  H01L23/53238 ,  H01L23/53266 ,  H10B12/30

摘要： A method for fabricating a semiconductor device structure includes forming a first conductive layer over a semiconductor substrate, and forming a dielectric layer over the first conductive layer. The method also includes replacing a portion of the dielectric layer with an energy removable layer, and performing an etching process to form a first opening in the energy removable layer and a second opening in the dielectric layer. The first opening is in a pattern-dense region and the second opening is in a pattern-loose region. The method further includes depositing a lining layer over the energy removable layer and the dielectric layer. The lining layer entirely fills the first opening to form a first conductive plug, and the lining layer partially fills the second opening.

公开(公告)号：US11823992B2

公开(公告)日：2023-11-21

申请号：US17484485

申请日：2021-09-24

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Tsu-Chieh Ai

IPC分类号： H01L21/768 ,  H01L23/498

CPC分类号： H01L23/49838 ,  H01L21/76838

摘要： The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom conductive layer positioned on the substrate; at least one bottom conductive protrusion positioned on the bottom conductive layer; an insulator layer positioned on the bottom conductive layer and the at least one bottom conductive protrusion; at least one bottom insulating protrusion protruding from the insulator layer towards the bottom conductive layer and adjacent to the at least one bottom conductive protrusion; and a top conductive layer positioned on the insulator layer. The bottom conductive layer, the at least one bottom conductive protrusion, the insulator layer, the at least one bottom insulating protrusion, and the top conductive layer together configure a capacitor structure.

公开(公告)号：US11823984B2

公开(公告)日：2023-11-21

申请号：US17497775

申请日：2021-10-08

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Tse-Yao Huang

IPC分类号： H01L23/485 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/485 ,  H01L21/76805 ,  H01L21/76897 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266

摘要： A method for fabricating a semiconductor device includes providing a substrate; sequentially forming a layer of first conductive material, a layer of second conductive material, a layer of third conductive material, and an anti-reflective coating layer over the substrate; performing a plug etch process to turn the layer of first conductive material into a bottom conductive layer on the substrate, turn the layer of second conductive material into a middle conductive layer on the bottom conductive layer, and turn the layer of third conductive material into a top conductive layer on the middle conductive layer; selectively forming an insulating covering layer on a sidewall of the middle conductive layer, wherein the bottom conductive layer, the middle conductive layer, the top conductive layer, and the insulating covering layer together configure a plug structure; and forming a first dielectric layer on the substrate and surrounding the plug structure.