公开(公告)号：US11995351B2

公开(公告)日：2024-05-28

申请号：US17515976

申请日：2021-11-01

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Joseph L Greathouse ,  Sean Keely ,  Alan D. Smith ,  Anthony Asaro ,  Ling-Ling Wang ,  Milind N Nemlekar ,  Hari Thangirala ,  Felix Kuehling

IPC: G06F3/00 ,  G06F3/06 ,  G06F13/28

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0679 ,  G06F13/28

Abstract: A method for hardware management of DMA transfer commands includes accessing, by a first DMA engine, a DMA transfer command and determining a first portion of a data transfer requested by the DMA transfer command. Transfer of a first portion of the data transfer by the first DMA engine is initiated based at least in part on the DMA transfer command. Similarly, a second portion of the data transfer by a second DMA engine is initiated based at least in part on the DMA transfer command. After transferring the first portion and the second portion of the data transfer, an indication is generated that signals completion of the data transfer requested by the DMA transfer command.

公开(公告)号：US11995008B2

公开(公告)日：2024-05-28

申请号：US17354806

申请日：2021-06-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra Nath Bhargava ,  James R. Magro ,  Kedarnath Balakrishnan

IPC: G06F13/16 ,  G11C11/4063

CPC classification number: G06F13/1642 ,  G11C11/4063

Abstract: A memory controller includes a command queue having an input for receiving memory access commands for a memory channel, and a number of entries for holding a predetermined number of memory access commands, and an arbiter that selects memory commands from the command queue for dispatch to one of a persistent memory and a DRAM memory coupled to the memory channel. The arbiter includes a first-tier sub-arbiter circuit coupled to the command queue for selecting candidate commands from among DRAM commands and persistent memory commands, and a second-tier sub-arbiter circuit coupled to the first-tier sub-arbiter circuit for receiving the candidate commands and selecting at least one command from among the candidate commands.

公开(公告)号：US20240168513A1

公开(公告)日：2024-05-23

申请号：US17990566

申请日：2022-11-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Nehal Patel

IPC: G06F1/10

CPC classification number: G06F1/10

Abstract: A disclosed technique includes clock gating a plurality of data elements of a first clock domain of a scan dump network; outputting data from a plurality of data elements of a second clock domain of the scan dump network; clock gating the plurality of data elements of the second clock domain; and outputting data from the plurality of data elements of the first clock domain.

公开(公告)号：US20240160364A1

公开(公告)日：2024-05-16

申请号：US17986623

申请日：2022-11-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ALEXANDRU DUTU ,  NUWAN JAYASENA ,  YASUKO ECKERT ,  NITI MADAN ,  SOORAJ PUTHOOR

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0659 ,  G06F3/0673

Abstract: An apparatus includes a memory controller that includes logic to receive a first memory request having a first request type and a second memory request having a second request type. The apparatus also includes a scheduling unit that includes logic to schedule an order of the first and second memory requests for execution based upon a first parameter value and a second parameter value. The first parameter value corresponds to a utility and energy cost for the first memory request and the second parameter value corresponds to a utility and energy cost for the second memory request.

公开(公告)号：US11984175B2

公开(公告)日：2024-05-14

申请号：US17855628

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Cai YongFeng

IPC: G06F9/445 ,  G11C17/00 ,  G11C29/04 ,  H03K19/20 ,  H03K19/21

CPC classification number: G11C29/04 ,  G11C17/00 ,  H03K19/20 ,  H03K19/21

Abstract: The disclosed method may include detecting, by a control circuit coupled to a first read only memory (ROM) device and a second ROM device, a failure of a first output signal from the first ROM device to a common output. The first ROM device is connected to the common output and the second ROM device is disconnected from the common output. The method also includes switching, by the control circuit in response to detecting the failure, the common output from the first ROM device to the second ROM device. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US11983560B2

公开(公告)日：2024-05-14

申请号：US17571374

申请日：2022-01-07

Applicant: Advanced Micro Devices, Inc.

Inventor： Li Peng ,  Jian Yang ,  Chi Tang

IPC: G06F9/48 ,  G06F9/54 ,  G06F12/0815 ,  G06F12/084 ,  G06F15/78

CPC classification number: G06F9/4881 ,  G06F9/542 ,  G06F12/0815 ,  G06F12/084 ,  G06F15/7807

Abstract: Systems, apparatuses, and methods for efficient parallel execution of multiple work units in a processor by reducing a number of memory accesses are disclosed. A computing system includes a processor core with a parallel data architecture. One or more of a software application and firmware implement matrix operations and support the broadcast of shared data to multiple compute units of the processor core. The application creates thread groups by matching compute kernels of the application with data items, and grouping the resulting work units into thread groups. The application assigns the thread groups to compute units based on detecting shared data among the compute units. Rather than send multiple read access to a memory subsystem for the shared data, a single access request is generated. The single access request includes information to identify the multiple compute units for receiving the shared data when broadcasted.

公开(公告)号：US20240152434A1

公开(公告)日：2024-05-09

申请号：US18502941

申请日：2023-11-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Srilatha Manne

IPC: G06F11/20

CPC classification number: G06F11/2023

Abstract: A device for disabling faulty cores using proxy virtual machines includes a processor, a faulty core, and a physical memory. The processor is responsible for executing a hypervisor that is configured to assign a proxy virtual machine to the faulty core. The assigned proxy virtual machine also includes a minimal workload. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US11978234B2

公开(公告)日：2024-05-07

申请号：US17135978

申请日：2020-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Pazhani Pillai ,  Mark A. Natale ,  Harish Kumar Kovalam Rajendran

IPC: G06T9/00 ,  G06T1/60

CPC classification number: G06T9/00 ,  G06T1/60

Abstract: A method and apparatus for processing color data includes storing fragment pointer and color data together in a color buffer. A delta color compression (DCC) key indicating the color data to fetch for processing is stored, and the fragment pointer and color data is fetched based upon the read DCC key for decompression.

公开(公告)号：US20240143445A1

公开(公告)日：2024-05-02

申请号：US17974981

申请日：2022-10-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Alicia Wen Ju Yurie Leong ,  William Robert Alverson ,  Joshua Taylor Knight ,  Jerry Anton Ahrens ,  Grant Evan Ley ,  Anil Harwani ,  Amitabh Mehra ,  Jayesh Hari Joshi

IPC: G06F11/14 ,  G11C29/52

CPC classification number: G06F11/1417 ,  G11C29/52

Abstract: Stability testing for memory overclocking is described. In accordance with the described techniques, operation of a memory with overclocked memory settings is testing during a boot up process of a computing device. Test results based on the testing are exposed via a user interface. The test results predict a stability of the memory over a subsequent time period if the memory is configured to operate with the overclocked memory settings.

公开(公告)号：US20240143056A1

公开(公告)日：2024-05-02

申请号：US18218463

申请日：2023-07-05

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ILC

Inventor： Greg SADOWSKI ,  Sriram Sundarm ,  Stephen Kushnir ,  William C. Brantley ,  Michael J. Schulte

IPC: G06F1/28 ,  G05F1/625

CPC classification number: G06F1/28 ,  G05F1/625

Abstract: A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.