公开(公告)号：US07883951B2

公开(公告)日：2011-02-08

申请号：US11556025

申请日：2006-11-02

Applicant: Justin K. Brask ,  Mark L. Doczy ,  Jack Kavalieros ,  Matthew V. Metz ,  Chris E. Barns ,  Uday Shah ,  Suman Datta ,  Christopher D. Thomas ,  Robert S. Chau

Inventor： Justin K. Brask ,  Mark L. Doczy ,  Jack Kavalieros ,  Matthew V. Metz ,  Chris E. Barns ,  Uday Shah ,  Suman Datta ,  Christopher D. Thomas ,  Robert S. Chau

IPC: H01L21/8238

CPC classification number: H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/1203 ,  H01L29/4975 ,  H01L29/66545 ,  Y10S438/926

Abstract: A semiconductor device and a method for forming it are described. The semiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.

Abstract translation: 对半导体装置及其形成方法进行说明。 半导体器件包括形成在衬底的第一部分上的金属NMOS栅电极和形成在衬底的第二部分上的硅化物PMOS栅电极。

公开(公告)号：US20100327317A1

公开(公告)日：2010-12-30

申请号：US12459262

申请日：2009-06-26

Applicant: Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Jack Kavalieros

Inventor： Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Jack Kavalieros

IPC: H01L29/12 ,  H01L29/772 ,  H01L21/336

CPC classification number: H01L29/78684 ,  H01L29/78603

Abstract: Embodiments of an apparatus and methods for providing germanium on insulator using a large bandgap barrier layer are generally described herein. Other embodiments may be described and claimed.

Abstract translation: 在此通常描述使用大带隙阻挡层在绝缘体上提供锗的装置和方法的实施例。 可以描述和要求保护其他实施例。

公开(公告)号：US07838373B2

公开(公告)日：2010-11-23

申请号：US12220985

申请日：2008-07-30

Applicant: Martin Giles ,  Titash Rakshit ,  Lucian Shifren ,  Jack Kavalieros ,  Willy Rachmady

Inventor： Martin Giles ,  Titash Rakshit ,  Lucian Shifren ,  Jack Kavalieros ,  Willy Rachmady

IPC: H01L21/336

CPC classification number: H01L29/6653 ,  H01L21/7682 ,  H01L23/485 ,  H01L23/5222 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A process includes planarizing a microelectronic device that includes a gate stack and adjacent trench contacts. The process also includes removing a gate spacer at the gate stack and replacing the gate spacer with a dielectric that results in a lowered overlap capacitance between the gate stack and an adjacent embedded trench contact.

Abstract translation: 一种方法包括平面化包括栅叠层和相邻沟槽触点的微电子器件。 该工艺还包括在栅极堆叠处移除栅极间隔物并用导电栅叠层和相邻的嵌入沟槽接触之间的重叠电容降低的电介质取代栅极间隔物。

公开(公告)号：US07825437B2

公开(公告)日：2010-11-02

申请号：US12006082

申请日：2007-12-28

Applicant: Ravi Pillarisetty ,  Suman Datta ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah

Inventor： Ravi Pillarisetty ,  Suman Datta ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah

IPC: H01L27/118

CPC classification number: H01L27/1104 ,  H01L27/11

Abstract: In general, in one aspect, a method includes forming N-diffusion and P-diffusion fins in a semiconductor substrate. A P-diffusion gate layer is formed over the semiconductor substrate and removed from the N-diffusion fins. A pass-gate N-diffusion gate layer is formed over the semiconductor substrate and removed from the P-diffusion fins and pull-down N-diffusion fins. A pull-down N-diffusion layer is formed over the semiconductor substrate.

Abstract translation: 通常，在一个方面，一种方法包括在半导体衬底中形成N-扩散和P-扩散翅片。 在半导体衬底上形成P扩散栅极层，并从N扩散鳍片上去除。 在半导体衬底上形成通过栅极的N扩散栅极层，并从P扩散鳍片和下拉的N扩散鳍片中去除。 在半导体衬底上形成下拉式N扩散层。

公开(公告)号：US07820512B2

公开(公告)日：2010-10-26

申请号：US12006063

申请日：2007-12-28

Applicant: Ravi Pillarisetty ,  Suman Datta ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah

Inventor： Ravi Pillarisetty ,  Suman Datta ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah

IPC: H01L21/8234 ,  H01L21/336 ,  H01L21/311

CPC classification number: H01L27/1104 ,  H01L27/0207

Abstract: In general, in one aspect, a method includes forming a semiconductor substrate having N-diffusion and P-diffusion regions. A gate stack is formed over the semiconductor substrate. A gate electrode hard mask is formed over the gate stack. The gate electrode hard mask is augmented around pass gate transistors with a spacer material. The gate stack is etched using the augmented gate electrode hard mask to form the gate electrodes. The gate electrodes around the pass gate have a greater length than other gate electrodes.

Abstract translation: 通常，一方面，一种方法包括形成具有N-扩散和P-扩散区域的半导体衬底。 在半导体衬底上形成栅叠层。 栅电极硬掩模形成在栅叠层上。 栅极电极硬掩模用隔离材料增加在通过栅极晶体管周围。 使用增强的栅极电极硬掩模蚀刻栅极堆叠以形成栅电极。 通过栅极周围的栅电极具有比其它栅电极更大的长度。

公开(公告)号：US07785958B2

公开(公告)日：2010-08-31

申请号：US12157796

申请日：2008-06-12

Applicant: Mark L. Doczy ,  Justin K. Brask ,  Jack Kavalieros ,  Uday Shah ,  Matthew V. Metz ,  Suman Datta ,  Ramune Nagisetty ,  Robert S. Chau

Inventor： Mark L. Doczy ,  Justin K. Brask ,  Jack Kavalieros ,  Uday Shah ,  Matthew V. Metz ,  Suman Datta ,  Ramune Nagisetty ,  Robert S. Chau

IPC: H01L21/8242

CPC classification number: H01L21/823842

Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, a trench within the first dielectric layer, and a second dielectric layer on the substrate. The second dielectric layer has a first part that is formed in the trench and a second part. After a first metal layer with a first workfunction is formed on the first and second parts of the second dielectric layer, part of the first metal layer is converted into a second metal layer with a second workfunction.

Abstract translation: 描述制造半导体器件的方法。 该方法包括在衬底上形成第一电介质层，在第一介电层内形成沟槽，在衬底上形成第二电介质层。 第二电介质层具有形成在沟槽中的第一部分和第二部分。 在第二电介质层的第一和第二部分上形成具有第一功函数的第一金属层之后，第一金属层的一部分被转换成具有第二功函数的第二金属层。

公开(公告)号：US20100163845A1

公开(公告)日：2010-07-01

申请号：US12319102

申请日：2008-12-30

Applicant: Niti Goel ,  Wilman Tsai ,  Jack Kavalieros

Inventor： Niti Goel ,  Wilman Tsai ,  Jack Kavalieros

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/7391 ,  H01L29/205 ,  H01L29/66356

Abstract: A TFET includes a source region (110, 210), a drain region (120, 220), a channel region (130, 230) between the source region and the drain region, and a gate region (140, 240) adjacent to the channel region. The source region contains a first compound semiconductor including a first Group III material and a first Group V material, and the channel region contains a second compound semiconductor including a second Group III material and a second Group V material. The drain region may contain a third compound semiconductor including a third Group III material and a third Group V material.

Abstract translation: TFET包括源极区（110,210），漏极区（120,220），在源极区和漏极区之间的沟道区（130,230）以及与该区域相邻的栅极区域（140,240） 渠道区域。 源极区域包含包含第一III族材料和第一V族材料的第一化合物半导体，并且沟道区域包含包含第二III族材料和第二V族材料的第二化合物半导体。 漏极区域可以包含第三化合物半导体，其包括第三III族材料和第三族V族材料。

公开(公告)号：US20100151669A1

公开(公告)日：2010-06-17

申请号：US12713432

申请日：2010-02-26

Applicant: Nick Lindert ,  Suman Datta ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Justin K. Brask ,  Robert S. Chau ,  Mark Bohr ,  Anand S. Murthy

Inventor： Nick Lindert ,  Suman Datta ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Justin K. Brask ,  Robert S. Chau ,  Mark Bohr ,  Anand S. Murthy

IPC: H01L21/28

CPC classification number: H01L29/7833 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

Abstract: A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.

Abstract translation: 栅极结构可以用作掩模以形成源区和漏区。 然后可以去除栅极结构以形成间隙，并且可以在间隙中形成间隔物以限定沟槽。 在将沟槽形成衬底的过程中，去除源极漏极区的一部分。 然后用外延材料填充衬底，并在其上形成新的栅极结构。 结果，可以实现更突然的源极漏极结。

公开(公告)号：US07704833B2

公开(公告)日：2010-04-27

申请号：US10925566

申请日：2004-08-25

Applicant: Nick Lindert ,  Suman Datta ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Justin K. Brask ,  Robert S. Chau ,  Mark Bohr ,  Anand S. Murthy

Inventor： Nick Lindert ,  Suman Datta ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Justin K. Brask ,  Robert S. Chau ,  Mark Bohr ,  Anand S. Murthy

IPC: H01L29/76

CPC classification number: H01L29/7833 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

Abstract: A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.

Abstract translation: 栅极结构可以用作掩模以形成源区和漏区。 然后可以去除栅极结构以形成间隙，并且可以在间隙中形成间隔物以限定沟槽。 在将沟槽形成衬底的过程中，去除源极漏极区的一部分。 然后用外延材料填充衬底，并在其上形成新的栅极结构。 结果，可以实现更突然的源极漏极结。

公开(公告)号：US20090230478A1

公开(公告)日：2009-09-17

申请号：US12049078

申请日：2008-03-14

Applicant: Ravi Pillarisetty ,  Brian Doyle ,  Titash Rakshit ,  Jack Kavalieros

Inventor： Ravi Pillarisetty ,  Brian Doyle ,  Titash Rakshit ,  Jack Kavalieros

IPC: H01L29/78 ,  H01L21/283

CPC classification number: H01L29/7855 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: Embodiments of an apparatus and methods for improving multi-gate device performance are generally described herein. Other embodiments may be described and claimed.

Abstract translation: 本文通常描述用于提高多栅极器件性能的装置和方法的实施例。 可以描述和要求保护其他实施例。