公开(公告)号：US11596052B2

公开(公告)日：2023-02-28

申请号：US16988756

申请日：2020-08-10

Applicant: Intel Corporation

Inventor： Wei Cheang Lau ,  Yew San Lim ,  Min Suet Lim

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/14 ,  H05K7/20 ,  H01L23/36

Abstract: The present disclosure generally relates to a computer circuit board having an integrated voltage regulator assembly that may include a heat sink and at least one voltage regulator module board. The heat sink may have a metal plate with at least one recess in which the voltage regulator module board may be attached. The voltage regulator module board is electrically coupled to a semiconductor package and the heat sink is thermally coupled to the semiconductor package. The computer circuit board is used in high-performance computing devices including computer workstations and computer servers.

公开(公告)号：US11589460B2

公开(公告)日：2023-02-21

申请号：US17090911

申请日：2020-11-06

Applicant: Intel Corporation

Inventor： Tin Poay Chuah ,  Min Suet Lim ,  Chee Chun Yee ,  Yew San Lim ,  Eng Huat Goh

IPC: H05K1/11 ,  H05K1/14

Abstract: A multilayer printed circuit board including a first printed circuit board portion, including a first inserting connector, including a plurality of contacts for creating a first removable bus connection; a second printed circuit board portion, including a second inserting connector, including a plurality of contacts for creating a second removable bus connection; a third printed circuit board portion, connected between the first printed circuit board portion and to the second printed circuit board portion, wherein a rigidity of the third printed circuit board portion is less than a rigidity of each of the first printed circuit board portion and the second printed circuit board portion; wherein the multilayer printed circuit board is foldable along the third printed circuit board portion and, if so folded, the first printed circuit board portion is arranged on top of the second printed circuit board portion.

公开(公告)号：US11552403B2

公开(公告)日：2023-01-10

申请号：US17512504

申请日：2021-10-27

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Min Suet Lim ,  Boon Ping Koh ,  Wil Choon Song ,  Khang Choong Yong

IPC: H01Q13/18 ,  H01Q1/38 ,  H01Q21/28

Abstract: Embodiments herein disclose techniques for apparatuses and methods for making a slot antenna on a PCB with a cutout. A PCB may include a metal layer. The metal layer may include a cavity to be a first radiating element of an antenna, and a slot to be a second radiating element of the antenna. In addition, the cavity may extend to be the cutout of the PCB through other layers of the PCB. The first and second radiating elements may provide a determined transmission frequency for the antenna. The metal layer may further include a portion of a transmission line of the antenna, and the transmission line is in contact with the cavity and the slot. A package may be affixed to the PCB, where a portion of the package may be within the cutout of the PCB. Other embodiments may be described and/or claimed.

公开(公告)号：US11487326B2

公开(公告)日：2022-11-01

申请号：US17088611

申请日：2020-11-04

Applicant: Intel Corporation

Inventor： Jeff Ku ,  Tin Poay Chuah ,  Yew San Lim ,  Min Suet Lim ,  Chee Chun Yee

IPC: G06F1/16 ,  G06F13/42 ,  H05K7/20 ,  G06F1/20

Abstract: The present disclosure relates to a docking station including a triangular prism shaped body, and a cradle proximal to a top section of the triangular prism shaped body for detachably receiving a mobile device, wherein the cradle may include a plurality of different connection interfaces to provide a selectable connection with a complementary connection interface of the mobile device.

公开(公告)号：US20220253119A1

公开(公告)日：2022-08-11

申请号：US17732792

申请日：2022-04-29

Applicant: Intel Corporation

Inventor： Rajashree Baskaran ,  Maruti Gupta Hyde ,  Min Suet Lim ,  Van Le ,  Hebatallah Saadeldeen

IPC: G06F1/3203 ,  G06F1/3234 ,  H01L25/16 ,  G06N3/063 ,  H01L25/065 ,  G06F1/20 ,  H01L25/18

Abstract: Methods and apparatus to provide power management for multi-die stacks using artificial intelligence are disclosed. An example integrated circuit (IC) package includes a computer processor unit (CPU) die, a memory die, inference engine circuitry within the CPU die, the inference engine circuitry to infer, based on a first machine learning model, a workload for at least one of the CPU die or the memory die, and power management engine circuitry within the CPU die, the power management engine circuitry distinct from the inference engine circuitry, the power management engine circuitry to adjust, based on a second machine learning model different than the first machine learning model, operational parameters associated with the at least one of the CPU die or the memory die, the inferred workload to be an input to the second machine learning model.

公开(公告)号：US11348909B2

公开(公告)日：2022-05-31

申请号：US16146445

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Maruti Gupta Hyde ,  Nageen Himayat ,  Linda Hurd ,  Min Suet Lim ,  Van Le ,  Gayathri Jeganmohan ,  Ankitha Chandran

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/367 ,  G06N3/08 ,  G06N3/063 ,  G06N3/04 ,  G06F1/3203 ,  H01L25/10 ,  G06F1/3296 ,  G06F1/3237 ,  G06F1/324 ,  H01L25/16 ,  G06F1/20 ,  G06F1/3206 ,  G06F1/3225 ,  G06F1/3287

Abstract: Methods and apparatus to implement efficient memory storage in multi-die packages are disclosed. An example multi-die package includes a multi-die stack including a first die and a second die. The second die is stacked on the first die. The multi-die package further includes a third die adjacent the multi-die stack. The multi-die package also includes a silicon-based connector to communicatively couple the multi-die stack and the third die. The silicon-based connector includes at least one of a logic circuit or a memory circuit.

公开(公告)号：US11320883B2

公开(公告)日：2022-05-03

申请号：US16146463

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Rajashree Baskaran ,  Maruti Gupta Hyde ,  Min Suet Lim ,  Van Le ,  Hebatallah Saadeldeen

IPC: G06F1/3203 ,  G06F1/3234 ,  H01L25/16 ,  G06N3/063 ,  H01L25/065 ,  G06F1/20 ,  H01L25/18 ,  G06N3/04 ,  G06N3/08

Abstract: Methods and apparatus to provide power management for multi-die stacks using artificial intelligence are disclosed. An example multi-die package includes a computer processor unit (CPU) die, a memory die stacked in vertical alignment with the CPU die, and artificial intelligence (AI) architecture circuitry to infer a workload for at least one of the CPU die or the memory die. The AI architecture circuitry is to manage power consumption of at least one of the CPU die or the memory die based on the inferred workload.

公开(公告)号：US11264315B2

公开(公告)日：2022-03-01

申请号：US15845531

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Min Suet Lim ,  Jiun Hann Sir ,  Hoay Tien Teoh ,  Jimmy Huat Since Huang

IPC: H01L23/498 ,  H05K1/18 ,  H01L21/56 ,  H01L23/522 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H05K3/34

Abstract: An electronic package with passive components located between a first substrate and a second substrate. The electronic package can include a first substrate including a device interface for communication with an electronic device. An interposer can be electrically coupled to the first substrate. A second substrate can be offset from the first substrate at a distance. The second substrate can be electrically coupled to the first substrate through the interposer. A passive component can be attached to one of the first substrate or the second substrate. The passive component can be located between the first substrate and the second substrate. A height of the passive component can be is less than the distance between the first substrate and the second substrate. The second substrate can include a die interface configured for communication with a die. The die interface can be communicatively coupled to the passive component.

公开(公告)号：US20210406085A1

公开(公告)日：2021-12-30

申请号：US17317679

申请日：2021-05-11

Applicant: Intel Corporation

Inventor： Divya Vijayaraghavan ,  Denica Larsen ,  Kooi Chi Ooi ,  Lady Nataly Pinilla Pico ,  Min Suet Lim

IPC: G06F9/50 ,  G06N3/08 ,  G06N3/04 ,  G06F11/30 ,  G06K9/62

Abstract: Methods, apparatus, systems, and articles of manufacture for allocating a workload to an accelerator using machine learning are disclosed. An example apparatus includes a workload attribute determiner to identify a first attribute of a first workload and a second attribute of a second workload. An accelerator selection processor causes at least a portion of the first workload to be executed by at least two accelerators, accesses respective performance metrics corresponding to execution of the first workload by the at least two accelerators, and selects a first accelerator of the at least two accelerators based on the performance metrics. A neural network trainer trains a machine learning model based on an association between the first accelerator and the first attribute of the first workload. A neural network processor processes, using the machine learning model, the second attribute to select one of the at least two accelerators to execute the second workload.

公开(公告)号：US20210397219A1

公开(公告)日：2021-12-23

申请号：US17359224

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Jeff Ku ,  Jose Oviedo Salazar ,  Twan Sing Loo ,  Khai Ern See ,  Min Suet Lim

IPC: G06F1/16

Abstract: Electronic devices with moveable display screens are described herein. An example electronic device includes a lid having a first display screen and a base. The lid is moveably coupled to the base. The base includes a housing having a top side and a bottom side, a physical keyboard to be accessed on the top side of the housing, and a second display screen moveable between a first position in which the keyboard is exposed and a second position in which the second display screen covers the keyboard.