公开(公告)号：US10304518B2

公开(公告)日：2019-05-28

申请号：US15633595

申请日：2017-06-26

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Chandra Mouli ,  Haitao Liu

IPC: G11C11/419 ,  G11C11/408 ,  H01L23/528 ,  H01L23/532 ,  H01L27/108

Abstract: Some embodiments include an apparatus which has a wordline coupled with a transistor gate, and which has a compensator line extending along the wordline and spaced from the wordline by a dielectric region. A driver is coupled with the wordline, and a controller is coupled with the compensator line. The wordline is coupled with access transistors, and is operated at a first voltage while the access transistors are in an OFF state. The compensator line is operated at a second voltage while the wordline is at the first voltage; with the second voltage being greater than the first voltage. The wordline is operated at a third voltage while the access transistors are in an ON state, and the compensator line is operated at a fourth voltage while the wordline is at the third voltage. The third voltage may or may not be greater than the fourth voltage.

公开(公告)号：US20190122737A1

公开(公告)日：2019-04-25

申请号：US16227874

申请日：2018-12-20

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Akira Goda

IPC: G11C16/26 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  G11C16/04 ,  H01L27/11573 ,  H01L27/11524 ,  G11C16/10 ,  H01L27/11556

CPC classification number: G11C16/26 ,  G11C7/1096 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a first group of conductive materials interleaved with a first group of dielectric materials, a first pillar extending through the first group of conductive materials and the first group of dielectric materials, memory cells located along the first pillar, a conductive contact coupled to one of the conductive materials, and a second pillar extending through a second group of conductive materials and a second group of dielectric materials. The second pillar includes a first portion coupled to a conductive region, a second portion, and a third portion, and a fourth portion coupled to the conductive contact. The second portion is located between the first and third portions. The second portion has a doping concentration less than a doping concentration of each of the first and fourth portions.

公开(公告)号：US20180342298A1

公开(公告)日：2018-11-29

申请号：US16036549

申请日：2018-07-16

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Haitao Liu ,  Changhyun Lee

IPC: G11C16/04 ,  H01L49/02 ,  H01L27/115 ,  H01L27/105 ,  G11C16/34 ,  G11C16/26 ,  G11C11/56 ,  G11C16/10 ,  G11C16/16 ,  G11C16/08

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  H01L27/1052 ,  H01L27/115 ,  H01L28/00

Abstract: Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.

公开(公告)号：US09953710B2

公开(公告)日：2018-04-24

申请号：US15583411

申请日：2017-05-01

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Jian Li ,  Chandra Mouli

IPC: H01L29/66 ,  G11C16/14 ,  H01L27/1158 ,  H01L27/11582 ,  H01L29/792 ,  G11C16/04 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/22

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/1158 ,  H01L27/11582 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/22 ,  H01L29/7926

Abstract: Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. Configurations shown can provide a reliable bias to a body region for memory operations such as erasing, and containment of charge in the body region during a boost operation.

公开(公告)号：US20170179031A1

公开(公告)日：2017-06-22

申请号：US14975746

申请日：2015-12-19

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Haitao Liu

IPC: H01L23/535 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/743 ,  H01L21/76816 ,  H01L21/76895 ,  H01L23/5283 ,  H01L28/00 ,  H01L29/41766 ,  H01L29/4236

Abstract: An electronic component of integrated circuitry comprises a substrate comprising at least two terminals. Material of one of the terminals has an upper surface. A conductive via extends elevationally into the material of the one terminal. The conductive via extends laterally into the material of the one terminal under the upper surface of the one terminal. Material of the one terminal is above at least some of the laterally extending conductive via. Other embodiments, including method embodiments, are disclosed.

公开(公告)号：US09640260B2

公开(公告)日：2017-05-02

申请号：US14320174

申请日：2014-06-30

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Jian Li ,  Chandra Mouli

IPC: H01L29/66 ,  G11C16/04 ,  H01L27/1158 ,  H01L27/11582 ,  H01L29/792 ,  G11C16/10

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/1158 ,  H01L27/11582 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/22 ,  H01L29/7926

Abstract: Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. Configurations shown can provide a reliable bias to a body region for memory operations such as erasing, and containment of charge in the body region during a boost operation.

公开(公告)号：US09437604B2

公开(公告)日：2016-09-06

申请号：US14069553

申请日：2013-11-01

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Roger W. Lindsay ,  Andrew Bicksler ,  Yongjun J Hu ,  Haitao Liu

IPC: H01L21/336 ,  H01L27/115 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L27/11556 ,  H01L23/5283 ,  H01L27/11524 ,  H01L29/456 ,  H01L29/66825 ,  H01L29/7926

Abstract: Methods for forming a string of memory cells, an apparatus having a string of memory cells, and a system are disclosed. A method for forming the string of memory cells comprises forming a metal silicide source material over a substrate. The metal silicide source material is doped. A vertical string of memory cells is formed over the metal silicide source material. A semiconductor material is formed vertically and adjacent to the vertical string of memory cells and coupled to the metal silicide source material.

Abstract translation: 公开了形成一串存储器单元的方法，具有一串存储单元的装置和系统。 一种用于形成存储单元串的方法包括在衬底上形成金属硅化物源材料。 掺杂金属硅化物源材料。 在金属硅化物源材料上形成垂直的存储单元串。 半导体材料垂直地形成并且与垂直的存储单元串相邻并且耦合到金属硅化物源材料。

公开(公告)号：US09437304B2

公开(公告)日：2016-09-06

申请号：US14857475

申请日：2015-09-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Akira Goda ,  Haitao Liu ,  Krishna Parat

IPC: G11C16/04 ,  G11C16/10 ,  H01L27/115

CPC classification number: G11C16/10 ,  G11C16/0483 ,  H01L27/11556 ,  H01L27/11582

Abstract: An embodiment of a method includes decreasing a difference of a voltage applied to a first select gate minus a voltage applied to a source while the first select gate is off, decreasing a difference of a voltage applied to a second select gate minus a voltage applied to a data line while the second select gate is off, and increasing a voltage of a signal applied to a selected access line that is coupled to an untargeted memory cell in a string of memory cells coupled to the first and second select gates to a program voltage after or substantially concurrently with decreasing the difference of the voltage applied to the first select gate minus the voltage applied to the source and with decreasing the difference of the voltage applied to the second select gate minus the voltage applied to the data line.

公开(公告)号：US09391206B2

公开(公告)日：2016-07-12

申请号：US14992966

申请日：2016-01-11

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Haitao Liu ,  Fawad Ahmed ,  Kamal M. Karda

IPC: H01L21/00 ,  H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0607 ,  H01L29/0692 ,  H01L29/42356 ,  H01L29/66795

Abstract: Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. The recesses have upper regions lined with liner material and have segments of semiconductor material exposed along lower regions. Semiconductor material is isotropically etched through the exposed segments which transforms the recesses into openings having wide lower regions beneath narrow upper regions. Gate dielectric material is formed along sidewalls of the openings. Gate material is formed within the openings and over regions of the semiconductor material between the openings. Insulative material is formed down the center of each opening and entirely through the gate material. A segment of gate material extends from one of the openings to the other, and wraps around a pillar of the semiconductor material between the openings. The segment is a gate of a transistor. Source/drain regions are formed on opposing sides of the gate.

公开(公告)号：US20160093709A1

公开(公告)日：2016-03-31

申请号：US14964923

申请日：2015-12-10

Applicant: Micron Technology, Inc.

Inventor： Deepak Pandey ,  Haitao Liu

IPC: H01L29/423 ,  H01L27/108 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/42376 ,  H01L21/28114 ,  H01L27/10805 ,  H01L27/10823 ,  H01L29/0847 ,  H01L29/4236 ,  H01L29/7827

Abstract: Some embodiments include transistor-containing constructions having gate material within an opening in a semiconductor material and spaced from the semiconductor material by gate dielectric material. The opening has a wide lower region beneath a narrow upper region. A saddle region of the gate dielectric material extends outwardly from a bottom of the opening and is along the semiconductor material beneath the opening. A saddle region of the gate material extends outwardly from the bottom of the opening and is along the gate dielectric material beneath the opening. Source/drain regions are within the semiconductor material along sides of the gate material. Some embodiments include memory arrays.