公开(公告)号：US20050110067A1

公开(公告)日：2005-05-26

申请号：US10901996

申请日：2004-07-30

申请人： Toshiharu Tanaka ,  Masaru Kito

发明人： Toshiharu Tanaka ,  Masaru Kito

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10867 ,  H01L27/10829

摘要： A semiconductor memory device includes a trench formed in the semiconductor substrate, a diffusion layer for a first electrode formed within the semiconductor substrate so as to be in contact with an inner surface of the trench, a capacitor insulating film formed on the diffusion layer, a conductive layer for a second electrode formed so as to bury a lower portion of the trench, a first insulating film formed on the conductive layer and along a side surface of the trench, a first conductive layer formed so as to bury an intermediate portion of the trench, a first contact layer formed so as to bury an upper portion of the trench, and a second contact layer formed on the surface of the semiconductor substrate so as to be in contact with the first contact layer.

摘要翻译： 半导体存储器件包括形成在半导体衬底中的沟槽，形成在半导体衬底内的与第一沟槽的内表面接触的第一电极的扩散层，形成在扩散层上的电容器绝缘膜， 用于第二电极的导电层，其形成为埋入沟槽的下部，形成在导电层上并沿着沟槽的侧表面的第一绝缘膜，形成为将第二绝缘膜的中间部分 沟槽，形成为埋入沟槽的上部的第一接触层和形成在半导体衬底的表面上以与第一接触层接触的第二接触层。

公开(公告)号：US08791464B2

公开(公告)日：2014-07-29

申请号：US12820371

申请日：2010-06-22

申请人： Tomoko Fujiwara ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Tomoko Fujiwara ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/7926

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a stacked structure, a semiconductor pillar, a memory layer and an outer insulating film. The stacked structure includes a plurality of electrode films and a plurality of interelectrode insulating films alternately stacked in a first direction. The semiconductor pillar pierces the stacked structure in the first direction. The memory layer is provided between the electrode films and the semiconductor pillar. The outer insulating film is provided between the electrode films and the memory layer. The device includes a first region and a second region. An outer diameter of the outer insulating film along a second direction perpendicular to the first direction in the first region is larger than that in the second region. A thickness of the outer insulating film along the second direction in the first region is thicker than that in the second region.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括堆叠结构，半导体柱，存储层和外部绝缘膜。 堆叠结构包括沿第一方向交替堆叠的多个电极膜和多个电极间绝缘膜。 半导体柱沿第一方向刺穿层叠结构。 存储层设置在电极膜和半导体柱之间。 外绝缘膜设置在电极膜和存储层之间。 该装置包括第一区域和第二区域。 沿着与第一区域的第一方向垂直的第二方向的外绝缘膜的外径大于第二区域的外径。 第一区域中沿着第二方向的外绝缘膜的厚度比第二区域厚。

公开(公告)号：US08653582B2

公开(公告)日：2014-02-18

申请号：US12724713

申请日：2010-03-16

申请人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： H01L29/788

CPC分类号： H01L27/11582 ,  H01L21/223 ,  H01L21/265 ,  H01L27/11578 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

摘要翻译： 一种非易失性半导体存储器件，包括：堆叠结构单元，包括在第一方向上交替地堆叠有多个电极膜的多个绝缘膜; 选择栅极电极，其沿所述第一方向堆叠在所述层叠结构单元上; 绝缘层，其沿所述第一方向堆叠在所述选择栅电极上; 第一半导体柱在第一方向上穿透层叠结构单元，选择栅电极和绝缘层，第一半导体柱的第一截面具有环形构造，第一横截面在垂直于 第一方向 第一核心单元，其被埋在第一半导体柱的内侧，第一芯单元从绝缘层的上表面凹入; 以及设置在所述第一芯单元上以接触所述第一芯单元的所述第一半导体柱的第一导电层。

公开(公告)号：US08605508B2

公开(公告)日：2013-12-10

申请号：US13463889

申请日：2012-05-04

申请人： Kiyotaro Itagaki ,  Yoshihisa Iwata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi ,  Akihiro Nitayama ,  Takashi Maeda ,  Tomoo Hishida

发明人： Kiyotaro Itagaki ,  Yoshihisa Iwata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi ,  Akihiro Nitayama ,  Takashi Maeda ,  Tomoo Hishida

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30

摘要： A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor. A control circuit is configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference. The certain potential difference is a potential difference that causes a GIDL current.

摘要翻译： 非易失性半导体存储装置包括：包括串联连接的多个存储单元的存储串; 第一选择晶体管，其一端连接到存储器串的一端; 第一布线，其一端连接到第一选择晶体管的另一端; 连接到第一选择晶体管的栅极的第二布线。 控制电路被配置为在保持第一布线的电压大于第二布线的电压一定电位差的同时，在擦除操作中提高第二布线和第一布线的电压。 一定的电位差是导致GIDL电流的电位差。

公开(公告)号：US08569133B2

公开(公告)日：2013-10-29

申请号：US13366509

申请日：2012-02-06

申请人： Masaru Kito ,  Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi

发明人： Masaru Kito ,  Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi

IPC分类号： H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device includes a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and select transistors, one of which is connected to each of ends of each of the memory strings. Each of the memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate, and a joining portion formed so as to join lower ends of the pair of columnar portions; a charge storage layer formed so as to surround a side surface of the columnar portions; and a first conductive layer formed so as to surround the side surface of the columnar portions and the charge storage layer, and configured to function as a control electrode of the memory cells. Each of the select transistors is provided with a second semiconductor layer extending upwardly from an upper surface of the columnar portions; and a second conductive layer formed so as to surround a side surface of the second semiconductor layer with a gap interposed, and configured to function as a control electrode of the select transistors.

摘要翻译： 非易失性半导体存储器件包括多个存储串，每个存储串具有串联连接的多个电可重写存储单元; 并选择晶体管，其中一个连接到每个存储器串的每一端。 每个存储器串都具有第一半导体层，该第一半导体层具有相对于基板在垂直方向上延伸的一对柱状部分，以及形成为连接该一对柱状部分的下端的接合部分; 形成为围绕所述柱状部的侧面的电荷存储层; 以及形成为围绕柱状部分的侧面和电荷存储层的第一导电层，并且被配置为用作存储单元的控制电极。 每个选择晶体管设置有从柱状部分的上表面向上延伸的第二半导体层; 以及第二导电层，其被形成为以间隔开的方式围绕所述第二半导体层的侧表面，并且被配置为用作所述选择晶体管的控制电极。

公开(公告)号：US08559221B2

公开(公告)日：2013-10-15

申请号：US13651019

申请日：2012-10-12

申请人： Masaru Kito ,  Hideaki Aochi

发明人： Masaru Kito ,  Hideaki Aochi

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： H01L27/11582 ,  H01L27/1157

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory unit and a control unit. The memory unit includes a charge storage film and a memory cell transistor. The transistor is provided for each of storage regions configured to store charge in the film. The control unit sets the transistors to an erase threshold by setting erase information in the regions; subsequently sets the transistors to thresholds corresponding to information having n values by programming the information having the n values to at least one of the regions in which the erase information is set; and controls information of at least one storage region before being programmed adjacent to the regions programmed with the information to have a value providing a threshold of the transistor nearer than the erase threshold to the thresholds corresponding to the information having the n values in the state of the transistors provided in the regions being set to the thresholds corresponding to the information having the n values.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括存储器单元和控制单元。 存储单元包括电荷存储膜和存储单元晶体管。 针对被配置为在电影中存储电荷的每个存储区域提供晶体管。 控制单元通过设置区域中的擦除信息将晶体管设置为擦除阈值; 随后通过将具有n个值的信息编程到设置有擦除信息的区域中的至少一个来将晶体管设置为对应于具有n个值的信息的阈值; 并且在与所述信息编程的区域相邻编程之前控制至少一个存储区域的信息，以使得具有提供比所述擦除阈值更接近的晶体管的阈值的值到与所述阈值的n值的信息相对应的阈值 设置在该区域中的晶体管被​​设置为对应于具有n值的信息的阈值。

公开(公告)号：US08440528B2

公开(公告)日：2013-05-14

申请号：US12638480

申请日：2009-12-15

申请人： Masaru Kito ,  Masaru Kidoh ,  Tomoko Fujiwara ,  Yosuke Komori ,  Megumi Ishiduki ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Ryouhei Kirisawa ,  Junya Matsunami ,  Hideaki Aochi

发明人： Masaru Kito ,  Masaru Kidoh ,  Tomoko Fujiwara ,  Yosuke Komori ,  Megumi Ishiduki ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Ryouhei Kirisawa ,  Junya Matsunami ,  Hideaki Aochi

IPC分类号： H01L21/336 ,  H01L21/4763

CPC分类号： H01L29/788 ,  G11C16/0458 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1156 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7889

摘要： A nonvolatile semiconductor memory device includes: forming a stacked body by alternately stacking a plurality of interlayer insulating films and a plurality of control gate electrodes; forming a through-hole extending in a stacking direction in the stacked body; etching a portion of the interlayer insulating film facing the through-hole via the through-hole to remove the portion; forming a removed portion; forming a first insulating film on inner faces of the through-hole and the portion in which the interlayer insulating films are removed; forming a floating gate electrode in the portion in which the interlayer insulating films are removed; forming a second insulating film so as to cover a portion of the floating gate electrode facing the through-hole; and burying a semiconductor pillar in the through-hole.

摘要翻译： 非易失性半导体存储器件包括：通过交替堆叠多个层间绝缘膜和多个控制栅电极来形成堆叠体; 在层叠体中形成沿堆叠方向延伸的通孔; 通过通孔蚀刻面向通孔的层间绝缘膜的一部分以除去该部分; 形成去除部分; 在通孔的内表面和除去层间绝缘膜的部分之间形成第一绝缘膜; 在除去层间绝缘膜的部分中形成浮栅电极; 形成第二绝缘膜，以覆盖面对通孔的浮栅电极的一部分; 并将半导体柱埋在通孔中。

公开(公告)号：US20130062685A1

公开(公告)日：2013-03-14

申请号：US13428111

申请日：2012-03-23

申请人： Naoki YASUDA ,  Masaru Kito

发明人： Naoki YASUDA ,  Masaru Kito

IPC分类号： H01L29/792

CPC分类号： H01L27/1157 ,  H01L21/28282 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/792 ,  H01L29/7926

摘要： According to one embodiment, a control gate is formed on the semiconductor substrate and includes a cylindrical through hole. A block insulating film, a charge storage film, a tunnel insulating film, and a semiconductor layer are formed on a side surface of the control gate inside the through hole. The tunnel insulating film comprises a first insulating film having SiO2 as a base material and containing an element that lowers a band gap of the base material by being added. A density and a density gradient of the element monotonously increase from the semiconductor layer toward the charge storage film.

公开(公告)号：US20130056815A1

公开(公告)日：2013-03-07

申请号：US13420745

申请日：2012-03-15

申请人： Megumi ISHIDUKI ,  Masaru Kidoh ,  Mitsuru Sato ,  Masaru Kito ,  Ryota Katsumata

发明人： Megumi ISHIDUKI ,  Masaru Kidoh ,  Mitsuru Sato ,  Masaru Kito ,  Ryota Katsumata

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7926 ,  H01L21/28282 ,  H01L27/11582 ,  H01L29/42344

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes: a first stacked body; a memory film; a first channel body layer provided inside the memory film; an interlayer insulating flm provided on the first stacked body; a second stacked body having a select gate electrode layer, and a second insulating layer; a gate insulating film provided on a side wall of a second hole communicating with the first hole and penetrating the second stacked body and the interlayer insulating flm in a stacking direction of the second stacked body; and a second channel body layer provided inside the gate insulating film in the second hole. A first pore diameter of the second hole at an upper end of the select gate electrode layer is smaller than a second pore diameter of the second hole at an lower end of the select gate electrode layer.

摘要翻译： 根据一个实施例，一种非易失性半导体存储器件包括：第一层叠体; 记忆膜; 设置在记忆膜内部的第一通道体层; 设置在第一层叠体上的层间绝缘膜; 具有选择栅电极层的第二层叠体和第二绝缘层; 栅极绝缘膜，设置在与所述第一孔连通的第二孔的侧壁上，并且在所述第二层叠体的层叠方向上贯通所述第二层叠体和所述层间绝缘膜; 以及设置在第二孔中的栅极绝缘膜内部的第二沟道体层。 选择栅电极层的上端的第二孔的第一孔径比选择栅电极层的下端的第二孔的第二孔径小。

公开(公告)号：US08372720B2

公开(公告)日：2013-02-12

申请号：US12679991

申请日：2008-12-09

申请人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi

发明人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi

IPC分类号： H01L21/336 ,  H01L29/792

CPC分类号： H01L27/11582 ,  G11C16/0483 ,  H01L27/1052 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/513

摘要： A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.