公开(公告)号：US09734097B2

公开(公告)日：2017-08-15

申请号：US13838296

申请日：2013-03-15

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Daniele Balluchi ,  Luca Porzio

IPC: G06F13/16 ,  G11C7/10

CPC classification number: G06F13/1689 ,  G06F13/161 ,  G11C7/106 ,  G11C7/1063 ,  G11C7/22 ,  G11C8/06 ,  G11C2207/2209 ,  G11C2207/2272 ,  G11C2207/229

Abstract: Apparatuses and methods for variable latency memory operations are disclosed herein. An example apparatus may include a memory configured to receive an activate command indicative of a type of a command during a first addressing phase and to receive the command during a second addressing phase. The memory may further be configured to provide information indicating that the memory is not available to perform a command responsive, at least in part, to receiving the command during a variable latency period and to provide information indicating that the memory is available to perform a command responsive, at least in part, to receiving the command after the variable latency period.

公开(公告)号：US20160351263A1

公开(公告)日：2016-12-01

申请号：US15170609

申请日：2016-06-01

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Corrado Villa

IPC: G11C16/10 ,  G11C13/00 ,  G11C16/34 ,  G11C16/26 ,  G11C16/08

CPC classification number: G11C16/10 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3436 ,  G11C16/3459 ,  G11C2213/79

Abstract: The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory controller and a method of performing the multiple access operations. In one aspect, the memory device includes a memory array comprising a plurality of memory cells and a memory controller. The memory controller is configured to receive a single command which specifies a plurality of memory access operations to be performed on the memory array. The memory controller is further configured to cause the specified plurality of memory access operations to be performed on the memory array.

公开(公告)号：US20160117108A1

公开(公告)日：2016-04-28

申请号：US14980819

申请日：2015-12-28

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Graziano Mirichigni

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0629 ,  G06F3/0685 ,  G06F12/0638 ,  G06F2212/2022 ,  G11C7/1015 ,  G11C7/1078 ,  G11C7/1084 ,  G11C16/102 ,  G11C16/32 ,  Y02D10/13

Abstract: A non volatile memory device includes a first buffer register configured to receive and store the data to be stored into the memory device provided via a memory bus. A command window is activatable for interposing itself for access to a memory matrix between the first buffer element and the memory matrix. The command window includes a second buffer element that stores data stored in or to be stored into a group of memory elements. A first data transfer means executes a first transfer of the data stored in the second buffer register into the first buffer register during a first phase of a data write operation started by the reception of a first command. A second data transfer means receives the data provided by the memory bus and modifies, based on the received data, the data stored in the first buffer register during a second phase of the data write operation started by the reception of a second command. The first transfer means execute a second transfer of the modified data stored in the first buffer register into the second buffer register during a third phase of the data write operation. The second transfer is executed in response to the reception of a signal received by the memory bus together with the second command.

Abstract translation: 非易失性存储器件包括：第一缓冲寄存器，用于接收和存储要存储到经由存储器总线提供的存储器件中的数据。 命令窗口可激活以插入其自身以访问第一缓冲元件和存储器矩阵之间的存储器矩阵。 命令窗口包括第二缓冲器元件，其存储存储在存储器或存储到一组存储器元件中的数据。 在通过接收第一命令开始的数据写入操作的第一阶段期间，第一数据传送装置执行将存储在第二缓冲寄存器中的数据的第一传送到第一缓冲寄存器。 第二数据传送装置接收由存储器总线提供的数据，并且在通过接收第二命令开始的数据写入操作的第二阶段期间，基于接收的数据修改存储在第一缓冲寄存器中的数据。 第一传送装置在数据写入操作的第三阶段期间执行将存储在第一缓冲寄存器中的修改数据的第二传送到第二缓冲寄存器。 响应于与第二命令一起接收由存储器总线接收的信号执行第二传送。

公开(公告)号：US20140369138A1

公开(公告)日：2014-12-18

申请号：US14472003

申请日：2014-08-28

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Graziano Mirichigni

IPC: G11C7/10

CPC classification number: G06F3/0604 ,  G06F3/0629 ,  G06F3/0685 ,  G06F12/0638 ,  G06F2212/2022 ,  G11C7/1015 ,  G11C7/1078 ,  G11C7/1084 ,  G11C16/102 ,  G11C16/32 ,  Y02D10/13

Abstract: A non volatile memory device includes a first buffer register configured to receive and store the data to be stored into the memory device provided via a memory bus. A command window is activatable for interposing itself for access to a memory matrix between the first buffer element and the memory matrix. The command window includes a second buffer element that stores data stored in or to be stored into a group of memory elements. A first data transfer means executes a first transfer of the data stored in the second buffer register into the first buffer register during a first phase of a data write operation started by the reception of a first command. A second data transfer means receives the data provided by the memory bus and modifies, based on the received data, the data stored in the first buffer register during a second phase of the data write operation started by the reception of a second command. The first transfer means execute a second transfer of the modified data stored in the first buffer register into the second buffer register during a third phase of the data write operation. The second transfer is executed in response to the reception of a signal received by the memory bus together with the second command.

Abstract translation: 非易失性存储器件包括：第一缓冲寄存器，用于接收和存储要存储到经由存储器总线提供的存储器件中的数据。 命令窗口可激活以插入其自身以访问第一缓冲元件和存储器矩阵之间的存储器矩阵。 命令窗口包括第二缓冲器元件，其存储存储在存储器或存储到一组存储器元件中的数据。 在通过接收第一命令开始的数据写入操作的第一阶段期间，第一数据传送装置执行将存储在第二缓冲寄存器中的数据的第一传送到第一缓冲寄存器。 第二数据传送装置接收由存储器总线提供的数据，并且在通过接收第二命令开始的数据写入操作的第二阶段期间，基于接收的数据修改存储在第一缓冲寄存器中的数据。 第一传送装置在数据写入操作的第三阶段期间执行将存储在第一缓冲寄存器中的修改数据的第二传送到第二缓冲寄存器。 响应于与第二命令一起接收由存储器总线接收的信号执行第二传送。

公开(公告)号：US08832392B2

公开(公告)日：2014-09-09

申请号：US14027088

申请日：2013-09-13

Applicant: Micron Technology, Inc.

Inventor： Marco Ferrario ,  Daniele Balluchi

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G11C7/10 ,  G06F12/02

CPC classification number: G06F12/02 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093

Abstract: Example embodiments of a non-volatile memory device may comprise receiving an index value at one or more input terminals of a memory device and storing the index value in a first register of the memory device. The first register may be implemented in a first clock domain, and the index value may identify a second register of the memory device implemented in a second clock domain.

Abstract translation: 非易失性存储器件的示例性实施例可包括在存储器件的一个或多个输入端接收索引值，并将该索引值存储在存储器件的第一寄存器中。 第一寄存器可以在第一时钟域中实现，并且索引值可以标识在第二时钟域中实现的存储器件的第二寄存器。

公开(公告)号：US20140022854A1

公开(公告)日：2014-01-23

申请号：US14034275

申请日：2013-09-23

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Graziano Mirichigni

IPC: G11C7/10

CPC classification number: G06F3/0604 ,  G06F3/0629 ,  G06F3/0685 ,  G06F12/0638 ,  G06F2212/2022 ,  G11C7/1015 ,  G11C7/1078 ,  G11C7/1084 ,  G11C16/102 ,  G11C16/32 ,  Y02D10/13

Abstract: A non volatile memory device includes a first buffer register configured to receive and store the data to be stored into the memory device provided via a memory bus. A command window is activatable for interposing itself for access to a memory matrix between the first buffer element and the memory matrix. The command window includes a second buffer element that stores data stored in or to be stored into a group of memory elements. A first data transfer means executes a first transfer of the data stored in the second buffer register into the first buffer register during a first phase of a data write operation started by the reception of a first command. A second data transfer means receives the data provided by the memory bus and modifies, based on the received data, the data stored in the first buffer register during a second phase of the data write operation started by the reception of a second command. The first transfer means execute a second transfer of the modified data stored in the first buffer register into the second buffer register during a third phase of the data write operation. The second transfer is executed in response to the reception of a signal received by the memory bus together with the second command.

Abstract translation: 非易失性存储器件包括：第一缓冲寄存器，用于接收和存储要存储到经由存储器总线提供的存储器件中的数据。 命令窗口可激活以插入其自身以访问第一缓冲元件和存储器矩阵之间的存储器矩阵。 命令窗口包括第二缓冲器元件，其存储存储在存储器或存储到一组存储器元件中的数据。 在通过接收第一命令开始的数据写入操作的第一阶段期间，第一数据传送装置执行将存储在第二缓冲寄存器中的数据的第一传送到第一缓冲寄存器。 第二数据传送装置接收由存储器总线提供的数据，并且在通过接收第二命令开始的数据写入操作的第二阶段期间，基于接收的数据修改存储在第一缓冲寄存器中的数据。 第一传送装置在数据写入操作的第三阶段期间执行将存储在第一缓冲寄存器中的修改数据的第二传送到第二缓冲寄存器。 响应于与第二命令一起接收由存储器总线接收的信号执行第二传送。

公开(公告)号：US20250156272A1

公开(公告)日：2025-05-15

申请号：US19021490

申请日：2025-01-15

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri ,  Marco Sforzin

IPC: G06F11/10

Abstract: A channel width can depend on a quantity of memory units (e.g., memory dice) that forms a channel as well as a size of the memory units. A memory system can operate with memory units configured to exchange (e.g., transfer to and/or from) data at a rate of smaller granularity that can provide more various options for channel widths, which can further allow a fine-tuned optimization of the memory system in association with its bandwidth and latency in transferring data from and/or to the memory units. The channels whose channel width is fine-tuned with such memory units can be further used to provide a reliability, availability, and serviceability (RAS) protection, such as a redundant array of independent disks (RAID) protection.

公开(公告)号：US20250077348A1

公开(公告)日：2025-03-06

申请号：US18776730

申请日：2024-07-18

Applicant: Micron Technology, Inc.

Inventor： Antonino Capri' ,  Daniele Balluchi ,  Joseph M. McCrate ,  Graziano Mirichigni ,  Danilo Caraccio ,  Marco Sforzin

IPC: G06F11/10

Abstract: A variety of applications can include a memory device implementing one or more caches or buffers integrated with a controller of the memory device to provide post package repair resources. The one or more caches or buffers can be separate from the media subsystem that stores user data for the memory device. Arrangements of the one or more caches or buffers can include the one or more caches or buffers structured between decoder-encoder arrangements of the memory device and the media subsystem of the memory device. Other arrangements of the one or more caches or buffers can include decoder-encoder arrangements of the memory device structured between the one or more caches or buffers and the media subsystem of the memory device. Combinations of arrangements may be implemented. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20250014629A1

公开(公告)日：2025-01-09

申请号：US18888626

申请日：2024-09-18

Applicant: Micron Technology, Inc.

Inventor： Dionisio Minopoli ,  Marco Sforzin ,  Daniele Balluchi

IPC: G11C11/406 ,  G11C11/4076

Abstract: A method including obtaining temperature values of a region of the non-volatile memory, each temperature value obtained at a given time instant, for each obtained temperature value at each given time instant, calculating the value of an operating function representative of an operating condition of the non-volatile memory, the value such operating function being time-dependent according to the temperature time-variation of the region of the non-volatile memory, summing subsequent computed values of the operating function to obtain an accumulated value being representative of an elapsed fraction of a time limit associated with the region of the non-volatile memory, comparing the accumulated value with a threshold value, and, based on the comparison, performing a management operation on the cells of the region of the non-volatile memory when the accumulated value has a magnitude equal or greater than the threshold value.

公开(公告)号：US12099457B2

公开(公告)日：2024-09-24

申请号：US17673731

申请日：2022-02-16

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Daniele Balluchi ,  Paolo Amato ,  Danilo Caraccio ,  Marco Sforzin

IPC: G06F13/16

CPC classification number: G06F13/1694

Abstract: Systems, apparatuses, and methods related to a controller for managing multiple types of memory are described. A controller includes a front end portion, a central controller portion, a back end portion, and a management unit can manage a first type of memory device that operates according to a first set of timing characteristics and a second type of memory device that operates according to a second set of timing characteristics. The central controller portion is configured to cause performance of a memory operation and comprises a cache memory to buffer data associated performance of the memory operation, a security component configured to encrypt the data before storing the data in the first type of memory device or the second type of memory device, and error correction code (ECC) circuitry to ECC encode and ECC decode the data.