公开(公告)号：US09087578B2

公开(公告)日：2015-07-21

申请号：US14041585

申请日：2013-09-30

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Riccardo Muzzetto

IPC: G11C13/00 ,  G11C7/14

CPC classification number: G11C13/004 ,  G11C7/02 ,  G11C7/04 ,  G11C7/14 ,  G11C13/0004 ,  G11C2013/0045 ,  G11C2013/0054

Abstract: This disclosure relates to generating a reference current for a memory device. In one aspect, a non-volatile memory device, such as a phase change memory device, can determine a value of a data digit, such as a bit, stored in a non-volatile memory cell based at least partly on the reference current. The reference current can be generated by mirroring a current at a node that is biased by a voltage bias. A configurable resistance circuit can have a resistance that is configurable. The resistance of the configurable resistance circuit can be in series between the node and a resistive non-volatile memory element. In some embodiments, a plurality of non-volatile memory elements can each be electrically connected in series between the resistance of the configurable resistance circuit and a corresponding selector.

Abstract translation: 本公开涉及生成用于存储器件的参考电流。 在一个方面，诸如相变存储器件的非易失性存储器件可以至少部分地基于参考电流来确定存储在非易失性存储器单元中的诸如位之类的数据位的值。 参考电流可以通过在由电压偏置偏置的节点处的电流进行镜像来产生。 可配置的电阻电路可以具有可配置的电阻。 可配置电阻电路的电阻可以串联在节点和电阻性非易失性存储器元件之间。 在一些实施例中，多个非易失性存储器元件可以各自在可配置电阻电路的电阻和相应的选择器之间串联电连接。

公开(公告)号：US09025392B1

公开(公告)日：2015-05-05

申请号：US14132390

申请日：2013-12-18

Applicant: Micron Technology, Inc.

Inventor： Efrem Bolandrina ,  Daniele Vimercati

IPC: G11C7/00 ,  G11C13/00

CPC classification number: G11C13/0033 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/79

Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes a memory cell, digit line driver, access line driver, clamping element, and control circuit. The memory cell and clamping element can be both coupled to a digit line. The control circuit can be configured to cause the clamping element to clamp the voltage of the digit line for a period of time while the digit line driver is caused to bias the digit line at a voltage level sufficient to enable selection of the memory cell. In addition, the control circuit can be configured to cause the access line driver to bias an access line coupled to memory cell when the voltage of the digit line is at the voltage level sufficient to enable selection of the memory cell.

Abstract translation: 在一个实施例中，公开了诸如存储器件的装置。 该装置包括存储单元，数字线驱动器，存取线驱动器，钳位元件和控制电路。 存储单元和钳位元件都可以耦合到数字线。 控制电路可以被配置为使得钳位元件在一段时间内钳位数字线的电压，同时使数字线驱动器以足以使得能够选择存储器单元的电压电平将数字线偏置。 此外，当数字线的电压处于足够使得能够选择存储器单元的电压电平时，控制电路可被配置为使得存取线驱动器偏置耦合到存储单元的存取线。

公开(公告)号：US20140241049A1

公开(公告)日：2014-08-28

申请号：US13775868

申请日：2013-02-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Daniele Vimercati ,  Riccardo Muzzetto

IPC: G11C7/12 ,  G11C5/14 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C7/062 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C29/025 ,  G11C29/028 ,  G11C2013/0052 ,  G11C2013/0054 ,  G11C2029/0409 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2207/063 ,  G11C2213/79

Abstract: Apparatuses, sense circuits, and methods for compensating for a voltage increase on a wordline in a memory is described. An example apparatus includes a bitline, a memory cell coupled to the bitline, a bipolar selector device coupled to the memory cell, a wordline coupled to the bipolar selector device, and a wordline driver coupled to the wordline. The apparatus further includes a model wordline circuit configured to model an impedance of the wordline and an impedance of the wordline driver, and a sense circuit coupled to the bitline and to the model wordline circuit. The sense circuit is configured to sense a state of the memory cell based on a cell current and provide a sense signal indicating a state of the memory cell. The sense circuit is further configured to adjust a bitline voltage responsive to an increase in wordline voltage as modeled by the model wordline circuit.

Abstract translation: 描述用于补偿存储器中的字线上的电压增加的装置，感测电路和方法。 示例性设备包括位线，耦合到位线的存储器单元，耦合到存储单元的双极选择器器件，耦合到双极选择器器件的字线和耦合到字线的字线驱动器。 该装置还包括：模型字线电路，被配置为模拟字线的阻抗和字线驱动器的阻抗，以及耦合到位线和模型字线电路的感测电路。 感测电路被配置为基于单元电流感测存储器单元的状态，并提供指示存储单元的状态的感测信号。 感测电路还被配置为响应于由模型字线电路建模的字线电压的增加来调整位线电压。

公开(公告)号：US20240419338A1

公开(公告)日：2024-12-19

申请号：US18749391

申请日：2024-06-20

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Jahanshir Javanifard ,  Daniele Vimercati

IPC: G06F3/06

Abstract: Methods, systems, and devices for data masking for memory are described. A memory device may set multiple data masking flags for associated memory array(s) at power-up. Each data masking flag may be associated with a respective page of memory cells and may indicate whether the data stored in the respective page is masked data, or whether the data is new, unmasked data. Data existing at a previous power-down may be masked until an initial write or activate command has been performed on the page after power-up, where the initial write or activate command may result in writing masked data, write data, or a combination thereof to the page. After previously stored data is overwritten to a page, the flag associated with the page may be reset, which may indicate that data stored at the page is available to be read.

公开(公告)号：US12131766B2

公开(公告)日：2024-10-29

申请号：US17675686

申请日：2022-02-18

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22

CPC classification number: G11C11/2259 ,  G11C11/221 ,  G11C11/2273

Abstract: Methods, systems, and devices for memory array with multiplexed select lines are described. In some cases, a memory cell of the memory device may include a storage component, a first transistor coupled with a word line, and a second transistor coupled with a first select line to selectively couple the memory cell with a first digit line. A third transistor may be coupled with the first digit line and a sense component common to a set of digit lines and a set of select lines. A second select line may be coupled with the third transistor and configured to couple the sense component with the first digit line and to couple the sense component with a second digit line. The sense component may determine a logic state stored by the memory cell based on the signal from the first digit line and the signal from the second digit line.

公开(公告)号：US12020749B2

公开(公告)日：2024-06-25

申请号：US17530676

申请日：2021-11-19

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H10B41/70

CPC classification number: G11C16/045 ,  G11C16/10 ,  G11C16/26 ,  H10B41/70

Abstract: The present disclosure includes apparatuses, methods, and systems for preventing parasitic current during program operations in memory. An embodiment includes a sense line, an access line, and a memory cell. The memory cell includes a first transistor having a floating gate and a control gate, wherein the control gate of the first transistor is coupled to the access line, and a second transistor having a control gate, wherein the control gate of the second transistor is coupled to the access line, a first node of the second transistor is coupled to the sense line, and a second node of the second transistor is coupled to the floating gate of the first transistor. The memory cell also includes a diode, or other rectifying element, coupled to the sense line and a node of the first transistor.

公开(公告)号：US11978493B2

公开(公告)日：2024-05-07

申请号：US18084884

申请日：2022-12-20

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22

CPC classification number: G11C11/2255 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2293

Abstract: Methods, systems, and devices for deck-level shunting in a memory device are described. A memory device may include memory arrays arranged in a stack of decks over a substrate, and a combination of deck selection circuitry and shunting circuitry may be distributed among the decks to leverage common substrate-based circuitry, such as logic or addressing circuitry. For example, each memory array of a stack may include a set of digit lines and deck selection circuitry, such as deck selection transistors or other switching circuitry, operable to couple the set of digit lines with a column decoder that may be shared among multiple decks. Each memory array of a stack also may include shunting circuitry, such as shunting transistors or other switching circuitry operable to couple the set of digit lines with a plate node, thereby equalizing a voltage across the memory cells of the respective memory array.

公开(公告)号：US11735234B2

公开(公告)日：2023-08-22

申请号：US17557825

申请日：2021-12-21

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Xinwei Guo

IPC: G11C27/02 ,  G11C7/06 ,  H03F3/45 ,  G11C11/16 ,  G11C11/15

CPC classification number: G11C7/062 ,  G11C11/15 ,  G11C11/1657 ,  H03F3/45076

Abstract: Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, an apparatus may include a memory cell, a differential amplifier having a first input node, a second input node, and an output node that is coupled with the first input node via a first capacitor, and a second capacitor coupled with the first input node. The apparatus may include a controller configured to cause the apparatus to bias the first capacitor, couple the memory cell with the first input node, and generate, at the output node, a sense signal based at least in part on biasing the first capacitor and coupling the memory cell with the first input node. The apparatus may also include a sense component configured to determine a logic state stored by the memory cell based at least in part on the sense signal.

公开(公告)号：US11699999B2

公开(公告)日：2023-07-11

申请号：US17571211

申请日：2022-01-07

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: H03K19/003 ,  G11C7/10 ,  H03K19/0185

CPC classification number: H03K19/00384 ,  G11C7/1057 ,  H03K19/00315 ,  H03K19/00361 ,  H03K19/018521

Abstract: An electronic device may include one or more output buffers each including a pair of final p-channel metal oxide semiconductor (PMOS) and n-channel metal oxide semiconductor (NMOS) transistors, a first pre-buffer to drive the PMOS transistor, and a second pre-buffer to drive the NMOS transistor. Each output buffer receives power from a pre-buffer supply filtering circuit, which may include a supply capacitor for stabilizing supply voltage, a low-pass first pre-buffer supply filter to filter the voltage supplied to the first pre-buffer, and a low-pass second pre-buffer supply filter the voltage supplied to the second pre-buffer.

公开(公告)号：US11688448B2

公开(公告)日：2023-06-27

申请号：US17470573

申请日：2021-09-09

Applicant: Micron Technology, Inc.

Inventor： Xinwei Guo ,  Daniele Vimercati

IPC: G11C11/22

CPC classification number: G11C11/2255 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2273

Abstract: Methods, systems, and devices for digit line management for a memory array are described. A memory array may include a plate that is common to a plurality of memory cells. Each memory cell associated with the common plate may be coupled with a respective digit line. One or more memory cells common to the plate may be accessed by concurrently selecting the plate and each digit line associated with the plate. Concurrent selection of all digit lines associated with the plate may be supported by shield lines between the selected digit lines. Additionally or alternatively, selection of all digit lines associated with the plate may be supported by improved sensing schemes and related amplifier configurations.