公开(公告)号：US20160365456A1

公开(公告)日：2016-12-15

申请号：US14739634

申请日：2015-06-15

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L29/788 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7883 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7889

Abstract: A semi-floating gate transistor is implemented as a vertical FET built on a silicon substrate, wherein the source, drain, and channel are vertically aligned, on top of one another. Current flow between the source and the drain is influenced by a control gate and a semi-floating gate. Front side contacts can be made to each one of the source, drain, and control gate terminals of the vertical semi-floating gate transistor. The vertical semi-floating gate FET further includes a vertical tunneling FET and a vertical diode. Fabrication of the vertical semi-floating gate FET is compatible with conventional CMOS manufacturing processes, including a replacement metal gate process. Low-power operation allows the vertical semi-floating gate FET to provide a high current density compared with conventional planar devices.

Abstract translation: 半浮栅晶体管被实现为内置于硅衬底上的垂直FET，其中源极，漏极和沟道彼此垂直对准。 源极和漏极之间的电流流动受到控制栅极和半浮栅的影响。 可以对垂直半浮栅晶体管的源极，漏极和控制栅极端子中的每一个进行正面接触。 垂直半浮栅FET还包括垂直隧道FET和垂直二极管。 垂直半浮栅FET的制造与常规CMOS制造工艺兼容，包括替代金属栅极工艺。 与传统的平面器件相比，低功耗操作允许垂直半浮栅FET提供高电流密度。

公开(公告)号：US20160211155A1

公开(公告)日：2016-07-21

申请号：US15085678

申请日：2016-03-30

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L21/67 ,  H01L21/677

CPC classification number: H01L21/3212 ,  B24B37/005 ,  H01L21/02074 ,  H01L21/6704 ,  H01L21/67207 ,  H01L21/67219 ,  H01L21/67253 ,  H01L21/67706 ,  H01L22/14 ,  H01L22/20

Abstract: CMP selectivity, removal rate, and uniformity are controlled both locally and globally by altering electric charge at the wafer surface. Surface charge characterization is performed by an on-board metrology module. Based on a charge profile map, the wafer can be treated in an immersion bath to impart a more positive or negative charge overall, or to neutralize the entire wafer before the CMP operation is performed. If charge hot spots are detected on the wafer, a charge pencil can be used to neutralize localized areas. One type of charge pencil bears a tapered porous polymer tip that is placed in close proximity to the wafer surface. Films present on the wafer absorb ions from, or surrender ions to, the charge pencil tip, by electrostatic forces. The charge pencil can be incorporated into a CMP system to provide an in-situ treatment prior to the planarization step or the slurry removal step.

公开(公告)号：US09385195B1

公开(公告)日：2016-07-05

申请号：US14675536

申请日：2015-03-31

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang

IPC: H01L29/745 ,  H01L27/148 ,  H01L21/00 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L29/10 ,  H01L29/49 ,  H01L29/20 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L27/10879 ,  B82Y10/00 ,  H01L21/28008 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823885 ,  H01L21/823892 ,  H01L27/0814 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/0653 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/66909 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/7855 ,  H01L29/7856 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696 ,  H01L31/0392 ,  H01L33/04 ,  H01L45/1233 ,  H01L2029/7858

Abstract: A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.

Abstract translation: 垂直隧道FET（TFET）为关键尺寸低于7nm的晶体管提供低功耗，高速开关性能。 垂直TFET使用全栅（GAA）器件结构，其具有在形成于硅衬底中的掺杂阱的表面上方延伸的圆柱形结构。 圆柱形结构包括从掺杂阱外延生长的下部漏极区域，沟道和上部源极区域。 该通道由本征硅制成，而源极和漏极区域原位掺杂。 环形栅极围绕通道，电容性地控制从所有侧面通过通道的电流。 源极可以通过前侧触点电接触，而漏极通过背面触点进行访问，该触点提供低接触电阻并且还用作散热器。 垂直TFET集成电路的可靠性通过将垂直TFET耦合到静电放电（ESD）二极管来增强。

公开(公告)号：US20160149051A1

公开(公告)日：2016-05-26

申请号：US14983276

申请日：2015-12-29

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/12 ,  H01L29/06

CPC classification number: H01L29/78618 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/127 ,  H01L29/165 ,  H01L29/401 ,  H01L29/413 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42392 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/66431 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/78696

Abstract: Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions.

Abstract translation: 金属量子点被并入到MOSFET阵列的掺杂源极和漏极区域中，以通过改变半导体晶体的能隙来帮助控制晶体管的性能。 在第一示例中，量子点被并入到离子掺杂的源极和漏极区域中。 在第二个例子中，量子点被并入外延掺杂的源区和漏区。

公开(公告)号：US09337087B1

公开(公告)日：2016-05-10

申请号：US14586688

申请日：2014-12-30

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Byoung Youp Kim ,  Walter Kleemeier

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/562 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76897 ,  H01L22/12 ,  H01L22/14 ,  H01L22/32 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/528 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments facilitate die protection for an integrated circuit. In one embodiment, a multilayer structure is formed in multiple levels and along the edges of a die to prevent and detect damages to the die. The multilayer structure includes a support layer, a first plurality of dielectric pillars overlying the support layer, a metal layer that fills spaces between the first plurality of dielectric pillars, an insulation layer overlying the first plurality of dielectric pillars and the metal layer, a second plurality of dielectric pillars overlying the insulation layer, and a second metal layer that fills spaces between the second plurality of dielectric pillars.

Abstract translation: 各种实施例便于集成电路的管芯保护。 在一个实施例中，多层结构形成在多个层次上并沿着模具的边缘，以防止和检测对模具的损坏。 所述多层结构包括支撑层，覆盖所述支撑层的第一多个介电柱，填充所述第一多个介电柱之间的空间的金属层，覆盖所述第一多个介电柱和所述金属层的绝缘层，第二 覆盖绝缘层的多个介电柱，以及填充第二多个介电柱之间的空间的第二金属层。

公开(公告)号：US20150325597A1

公开(公告)日：2015-11-12

申请号：US14802996

申请日：2015-07-17

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L27/12 ,  H01L27/092 ,  H01L27/112 ,  H01L29/78 ,  H01L23/528 ,  H01L27/11 ,  H01L29/161

CPC classification number: H01L27/1211 ,  H01L21/266 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/845 ,  H01L23/528 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/11213 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7838 ,  H01L29/7849 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

Abstract translation: 适用于SRAM存储器阵列的单栅极和双栅极FinFET器件具有由半导体衬底上的单个邻接层的部分形成的各自的鳍片，源极区域和漏极区域，因此不需要STI。 FinFET的一对可以配置为从属栅极器件，其中相邻通道由公共栅极控制，或者作为独立栅极器件，其中一个通道由两个栅极控制。 耦合多个FinFET器件的金属互连由与栅电极相同的材料制成。 这种结构和材料的共同点有助于降低制造高密度存储器阵列的成本。

公开(公告)号：US20150279780A1

公开(公告)日：2015-10-01

申请号：US14314945

申请日：2014-06-25

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Richard Stephen Wise ,  Akil K. Sutton ,  Terry Allen SPOONER ,  Nicole A. SAULNIER

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76835 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wavy line interconnect structure that accommodates small metal lines and enlarged diameter vias is disclosed. The enlarged diameter vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. The enlarged diameter vias make direct contact with at least three sides of the underlying metal lines, and can be aligned asymmetrically with respect to the metal line to increase the packing density of the metal pattern. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. An interconnect structure having enlarged diameter vias can also feature air gaps to reduce the chance of dielectric breakdown. By allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.

Abstract translation: 公开了一种容纳小金属线和扩大直径通孔的波浪线互连结构。 扩大的直径通孔可以使用自对准双镶嵌工艺形成，而不需要单独的通孔光刻掩模。 扩大的直径通孔与下面的金属线的至少三侧直接接触，并且可以相对于金属线不对称地对准，以增加金属图案的堆积密度。 所得到的通孔具有相对容易填充的纵横比，而较大的通孔覆盖区提供低通孔电阻。 具有扩大的直径通孔的互连结构也可以具有气隙，以减少电介质击穿的机会。 通过允许通孔占地面积超过金属线宽度的最小尺寸，可以为进一步的工艺世代清除路径，以继续将金属线收缩到低于10nm的尺寸。

公开(公告)号：US09111801B2

公开(公告)日：2015-08-18

申请号：US13856985

申请日：2013-04-04

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L21/04 ,  H01L27/12 ,  H01L29/66 ,  H01L21/84 ,  H01L27/11

CPC classification number: H01L27/1211 ,  H01L21/266 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/845 ,  H01L23/528 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/11213 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7838 ,  H01L29/7849 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuit devices and fabrication techniques. A semiconductor device fabrication method may include doping, in a same processing step, first and second portions of a substrate of an integrated circuit. The first portion corresponds to a doped region of a semiconductor device. The second portion corresponds to a via contact. The method may further include, after the doping, forming the gate of the semiconductor device.

Abstract translation: 集成电路器件和制造技术。 半导体器件制造方法可以包括在相同的处理步骤中掺杂集成电路的衬底的第一和第二部分。 第一部分对应于半导体器件的掺杂区域。 第二部分对应于通孔接触。 该方法还可以包括在掺杂之后形成半导体器件的栅极。

公开(公告)号：US20150087205A1

公开(公告)日：2015-03-26

申请号：US14035281

申请日：2013-09-24

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: B24B37/005

CPC classification number: B24B37/005 ,  B24B27/0076 ,  B24B49/04

Abstract: An adaptive uniform polishing system is equipped with feedback control to apply localized adjustments during a polishing operation. The adaptive uniform polishing system disclosed has particular application to the semiconductor industry. Such an adaptive uniform polishing system includes a rotatable head that holds a semiconductor wafer, and a processing unit structured to be placed in contact with an exposed surface of the wafer. The processing unit includes a rotatable macro-pad and a plurality of rotatable micro-pads that can polish different portions of the exposed surface at different rotation speeds and pressures. Thus, uniformity across the exposed surface can be enhanced by applying customized treatments to different areas. Customized treatments can include the use of different pad materials and geometries. Parameters of the adaptive uniform polishing system are programmable, based on in-situ data or data from other operations in a fabrication process, using advanced process control.

Abstract translation: 自适应均匀抛光系统配备有反馈控制，以在抛光操作期间应用局部调整。 所公开的自适应均匀抛光系统特别适用于半导体工业。 这种自适应均匀抛光系统包括保持半导体晶片的可旋转头部和被构造成与晶片的暴露表面接触的处理单元。 处理单元包括可旋转的宏观垫和多个可旋转的微垫，其可以以不同的转速和压力抛光暴露表面的不同部分。 因此，通过将定制的处理应用于不同的区域，可以增强暴露表面的均匀性。 定制处理可以包括使用不同的垫材料和几何形状。 自适应均匀抛光系统的参数是可编程的，基于在制造过程中的其他操作的原位数据或数据，使用先进的过程控制。

公开(公告)号：US20150005610A1

公开(公告)日：2015-01-01

申请号：US13931138

申请日：2013-06-28

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: A61B5/04 ,  A61B5/00

CPC classification number: A61B5/04001 ,  A61B5/6877 ,  A61B5/688 ,  B82Y30/00 ,  G01N27/4145 ,  Y10T29/4913

Abstract: It is recognized that, because of its unique properties, graphene can serve as an interface with biological cells that communicate by an electrical impulse, or action potential. Responding to a sensed signal can be accomplished by coupling a graphene sensor to a low power digital electronic switch that is activatable by the sensed low power electrical signals. It is further recognized that low power devices such as tunneling diodes and TFETs are suitable for use in such biological applications in conjunction with graphene sensors. While tunneling diodes can be used in diagnostic applications, TFETs, which are three-terminal devices, further permit controlling the voltage on one cell according to signals received by other cells. Thus, by the use of a biological sensor system that includes graphene nanowire sensors coupled to a TFET, charge can be redistributed among different biological cells, potentially with therapeutic effects.

Abstract translation: 人们认识到，由于其独特的性质，石墨烯可以作为通过电脉冲或动作电位进行通信的生物细胞的界面。 响应感测的信号可以通过将石墨烯传感器耦合到由感测的低功率电信号激活的低功率数字电子开关来实现。 进一步认识到，诸如隧道二极管和TFET的低功率器件适用于与石墨烯传感器相结合的这种生物学应用中。 虽然隧道二极管可以用于诊断应用，但是作为三端子器件的TFET还允许根据其他单元接收的信号来控制一个单元上的电压。 因此，通过使用包括耦合到TFET的石墨烯纳米线传感器的生物传感器系统，电荷可以在不同的生物细胞中重新分布，潜在地具有治疗效果。