公开(公告)号：US09577036B1

公开(公告)日：2017-02-21

申请号：US14939310

申请日：2015-11-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/764 ,  H01L21/823431 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor device and a semiconductor fin on the semiconductor substrate, in which the semiconductor fin has a fin isolation structure at a common boundary that is shared by the two cells. The fin isolation structure has an air gap extending from a top of the semiconductor fin to a stop layer on the semiconductor substrate. The air gap divides the semiconductor fin into two portions of the semiconductor fin. The fin isolation structure includes a dielectric cap layer capping a top of the air gap.

Abstract translation: 半导体器件包括在半导体衬底上的半导体器件和半导体鳍片，其中半导体鳍片具有在由两个单元共享的公共边界处的鳍片隔离结构。 翅片隔离结构具有从半导体鳍片的顶部延伸到半导体衬底上的停止层的气隙。 气隙将半导体翅片分成半导体翅片的两个部分。 翅片隔离结构包括覆盖气隙顶部的电介质盖层。

公开(公告)号：US09502567B2

公开(公告)日：2016-11-22

申请号：US14621805

申请日：2015-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/00 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/785

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a fin structure formed over the substrate. The semiconductor structure further includes an isolation structure formed around the fin structure and a gate structure formed across the fin structure. In addition, the gate structure includes a first portion formed over the fin structure and a second portion formed over the isolation structure, and the second portion of the gate structure includes an extending portion extending into the isolation structure.

Abstract translation: 提供半导体结构及其形成方法。 该半导体结构包括在基板上形成的基板和翅片结构。 半导体结构还包括形成在翅片结构周围的隔离结构和横跨翅片结构形成的栅极结构。 此外，栅极结构包括形成在鳍状结构上的第一部分和形成在隔离结构上的第二部分，并且栅极结构的第二部分包括延伸到隔离结构中的延伸部分。

公开(公告)号：US09461043B1

公开(公告)日：2016-10-04

申请号：US14754627

申请日：2015-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Wei-Ting Chen

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/12

CPC classification number: H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate, a first gate, a second gate, and an insulating structure. The substrate includes a first fin and a second fin. The first gate is disposed over the first fin. The second gate is disposed over the second fin. A gap is formed between the first gate and the second gate, and the gap gets wider toward the substrate. The insulating structure is disposed in the gap. The insulating structure has a top surface and a bottom surface opposite to each other. The bottom surface faces the substrate. An edge of the top surface facing the first gate is curved inward the top surface.

Abstract translation: 半导体器件包括衬底，第一栅极，第二栅极和绝缘结构。 基板包括第一翅片和第二翅片。 第一个门被放置在第一个鳍上。 第二个门设置在第二个翅片上。 在第一栅极和第二栅极之间形成间隙，并且间隙朝向衬底变宽。 绝缘结构设置在间隙中。 绝缘结构具有彼此相对的顶表面和底表面。 底面朝向基板。 面向第一门的顶面的边​​缘在顶面向内弯曲。

公开(公告)号：US09406680B1

公开(公告)日：2016-08-02

申请号：US14698831

申请日：2015-04-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Jr-Jung Lin ,  Chih-Han Lin

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/16 ,  H01L21/306 ,  H01L29/161 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795

Abstract: A semiconductor device includes a Fin FET transistor. The Fin FET transistor includes a first fin structure extending in a first direction, a gate stack and a source and a drain. The gate stack includes a gate electrode layer and a gate dielectric layer, covers a portion of the fin structure and extends in a second direction perpendicular to the first direction. Each of the source and drain includes a stressor layer disposed over the fin structure. The stressor layer applies a stress to a channel layer of the fin structure under the gate stack. The stressor layer penetrates under the gate stack. A vertical interface between the stressor layer and the fin structure under the gate stack in a third direction perpendicular to the first and second directions includes a flat portion.

Abstract translation: 半导体器件包括Fin FET晶体管。 鳍FET晶体管包括沿第一方向延伸的第一鳍结构，栅极堆叠以及源极和漏极。 栅堆叠包括栅极电极层和栅极电介质层，覆盖翅片结构的一部分并且沿垂直于第一方向的第二方向延伸。 源极和漏极中的每一个包括设置在鳍结构上的应力层。 应力层对栅叠层下的鳍结构的沟道层施加应力。 应力层穿过栅极叠层。 在垂直于第一和第二方向的第三方向上的应力层和翅片结构之间的垂直界面包括平坦部分。

公开(公告)号：US09331074B1

公开(公告)日：2016-05-03

申请号：US14611159

申请日：2015-01-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/70 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/31055 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6681

Abstract: A semiconductor device includes first and second Fin FET transistors and a separation plug made of an insulating material and disposed between the first and second Fin FET transistors. The first Fin FET transistor includes a first fin structure extending in a first direction, a first gate dielectric formed over the first fin structure and a first gate electrode formed over the first gate dielectric and extending a second direction perpendicular to the first direction. The second Fin FET transistor includes a second fin structure, a second gate dielectric formed over the second fin structure and a second gate electrode formed over the first gate dielectric and extending the second direction. In a cross section along the second direction and across the first gate electrode, the second gate electrode and the separation plug, the separation plug has a tapered shape having a top size smaller than a bottom size.

Abstract translation: 半导体器件包括第一和第二Fin FET晶体管和由绝缘材料制成并分布在第一和第二Fin FET晶体管之间的分离插头。 第一Fin FET晶体管包括在第一方向上延伸的第一鳍结构，形成在第一鳍结构上的第一栅极电介质和形成在第一栅极电介质上并且垂直于第一方向延伸的第二方向的第一栅电极。 第二鳍FET晶体管包括第二鳍结构，形成在第二鳍结构上的第二栅极电介质和形成在第一栅极电介质上并延伸第二方向的第二栅电极。 在沿着第二方向并横跨第一栅电极，第二栅电极和分离插塞的横截面中，分离插塞具有顶部尺寸小于底部尺寸的锥形形状。

公开(公告)号：US12261213B2

公开(公告)日：2025-03-25

申请号：US17814779

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin

IPC: H01L29/78 ,  H01L21/027 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

Abstract: A method includes simultaneously forming a first dummy gate stack and a second dummy gate stack on a first portion and a second portion of a protruding fin, simultaneously removing a first gate electrode of the first dummy gate stack and a second gate electrode of the second dummy gate stack to form a first trench and a second trench, respectively, forming an etching mask, wherein the etching mask fills the first trench and the second trench, patterning the etching mask to remove the etching mask from the first trench, removing a first dummy gate dielectric of the first dummy gate stack, with the etching mask protecting a second dummy gate dielectric of the second dummy gate stack from being removed, and forming a first replacement gate stack and a second replacement gate stack in the first trench and the second trench, respectively.

公开(公告)号：US12125751B2

公开(公告)日：2024-10-22

申请号：US18157352

申请日：2023-01-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Jr-Jung Lin

IPC: H01L23/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a substrate, a fin protruding from the substrate, and a gate stack over the substrate and engaging the fin. The fin having a first end and a second end. The semiconductor device also includes a dielectric layer abutting the first end of the fin and spacer features disposed on sidewalls of the gate stack and on a top surface of the dielectric layer.

公开(公告)号：US12080770B2

公开(公告)日：2024-09-03

申请号：US18065166

申请日：2022-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/324 ,  H01L21/768 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285

CPC classification number: H01L29/41791 ,  H01L21/265 ,  H01L21/324 ,  H01L21/76814 ,  H01L21/76897 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/28518 ,  H01L21/76804 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device and method of manufacture are provided. A source/drain region is formed next to a spacer, which is adjacent to a gate electrode. An implantation is performed through an implantation mask into the source/drain region as well as the first spacer, forming an implantation region within the spacer.

公开(公告)号：US20240290867A1

公开(公告)日：2024-08-29

申请号：US18655832

申请日：2024-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/42368 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device includes a fin extending from a substrate, a gate stack over and along a sidewall of the fin, a spacer along a first sidewall of the gate stack and the sidewall of the fin, a dummy gate material along the sidewall of the fin, wherein the dummy gate material is between the spacer and the gate stack, and a first epitaxial source/drain region in the fin and adjacent the gate stack.

公开(公告)号：US12009406B2

公开(公告)日：2024-06-11

申请号：US17345188

申请日：2021-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/42368 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device includes a fin extending from a substrate, a gate stack over and along a sidewall of the fin, a spacer along a first sidewall of the gate stack and the sidewall of the fin, a dummy gate material along the sidewall of the fin, wherein the dummy gate material is between the spacer and the gate stack, and a first epitaxial source/drain region in the fin and adjacent the gate stack.